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Searched refs:spx5_rmw (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_port.c352 spx5_rmw(0, in sparx5_port_disable()
358 spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS, in sparx5_port_disable()
364 spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1), in sparx5_port_disable()
374 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
386 spx5_rmw(0, in sparx5_port_disable()
422 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
441 spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0), in sparx5_port_disable()
447 spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0), in sparx5_port_disable()
529 spx5_rmw(BIT(inst), in sparx5_port_mux_set()
536 spx5_rmw(PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(1) | in sparx5_port_mux_set()
[all …]
Dsparx5_fdma.c71 spx5_rmw(FDMA_XTR_CFG_XTR_FIFO_WM_SET(31), FDMA_XTR_CFG_XTR_FIFO_WM, in sparx5_fdma_rx_activate()
76 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), FDMA_PORT_CTRL_XTR_STOP, in sparx5_fdma_rx_activate()
80 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_rx_activate()
93 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_rx_deactivate()
97 spx5_rmw(0, BIT(fdma->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA, in sparx5_fdma_rx_deactivate()
101 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(1), FDMA_PORT_CTRL_XTR_STOP, in sparx5_fdma_rx_deactivate()
122 spx5_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), FDMA_PORT_CTRL_INJ_STOP, in sparx5_fdma_tx_activate()
132 spx5_rmw(0, BIT(tx->fdma.channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE, in sparx5_fdma_tx_deactivate()
205 spx5_rmw(BIT(fdma->channel_id), in sparx5_fdma_napi_callback()
373 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_fdma_injection_mode()
[all …]
Dsparx5_vlan.c29 spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1), in sparx5_vlan_init()
36 spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid), in sparx5_vlan_init()
47 spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) | in sparx5_vlan_port_setup()
127 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_update_mask()
131 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_update_mask()
135 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_update_mask()
234 spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid), in sparx5_vlan_port_apply()
Dsparx5_ptp.c282 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_get_hwtimestamp()
340 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
367 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), in sparx5_ptp_irq_handler()
420 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)), in sparx5_ptp_adjfine()
429 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0), in sparx5_ptp_adjfine()
448 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_settime64()
464 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | in sparx5_ptp_settime64()
487 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | in sparx5_ptp_gettime64()
525 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) | in sparx5_ptp_adjtime()
537 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) | in sparx5_ptp_adjtime()
[all …]
Dsparx5_mirror.c40 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
42 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
54 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_del()
56 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_del()
82 spx5_rmw(ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(dir), in sparx5_mirror_dir_set()
91 spx5_rmw(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(portno), in sparx5_mirror_monitor_set()
Dsparx5_main.c391 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), in sparx5_init_switchcore()
396 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), in sparx5_init_switchcore()
491 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | in sparx5_init_coreclock()
508 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), in sparx5_init_coreclock()
513 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
518 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
523 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
529 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), in sparx5_init_coreclock()
534 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET in sparx5_init_coreclock()
540 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), in sparx5_init_coreclock()
[all …]
Dsparx5_psfp.c75 spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID, in sparx5_isdx_conf_set()
78 spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX, in sparx5_isdx_conf_set()
121 spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) | in sparx5_psfp_sf_set()
150 spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) | in sparx5_psfp_sg_set()
330 spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1), in sparx5_psfp_init()
Dsparx5_police.c32 spx5_rmw(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(max_pup_tokens), in sparx5_policer_service_conf_set()
36 spx5_rmw(ANA_AC_SDLB_THRES_THRES_SET(thres), ANA_AC_SDLB_THRES_THRES, in sparx5_policer_service_conf_set()
Dsparx5_qos.c248 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_lg_conf_set()
256 spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first), in sparx5_lg_conf_set()
338 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer), in sparx5_shaper_conf_set()
342 spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE, in sparx5_shaper_conf_set()
367 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | in sparx5_dwrr_conf_set()
373 spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count), in sparx5_dwrr_conf_set()
378 spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]), in sparx5_dwrr_conf_set()
Dsparx5_vcap_impl.c1546 spx5_rmw(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1553 spx5_rmw(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1560 spx5_rmw(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(value), in sparx5_vcap_is0_set_port_keyset()
1635 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1642 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1646 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1653 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1658 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1665 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(value), in sparx5_vcap_is2_set_port_keyset()
1728 spx5_rmw(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(value), in sparx5_vcap_es2_set_port_keyset()
[all …]
Dsparx5_packet.c296 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_injection_timeout()
328 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1), in sparx5_manual_injection_mode()
334 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0), in sparx5_manual_injection_mode()
341 spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0), in sparx5_manual_injection_mode()
Dsparx5_calendar.c211 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), in sparx5_config_auto_calendar()
222 spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */ in sparx5_config_auto_calendar()
234 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8), in sparx5_config_auto_calendar()
543 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), in sparx5_dsm_calendar_update()
547 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]), in sparx5_dsm_calendar_update()
Dsparx5_sdlb.c61 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(0), in sparx5_sdlb_group_disable()
68 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(1), in sparx5_sdlb_group_enable()
Dsparx5_mactable.c482 spx5_rmw(LRN_AUTOAGE_CFG_UNIT_SIZE_SET(2) | /* 10 ms */ in sparx5_set_ageing()
Dsparx5_ethtool.c1162 spx5_rmw(ANA_AC_PORT_SGE_CFG_MASK_SET(0xf0f0), in sparx5_config_stats()
1176 spx5_rmw(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(1) | in sparx5_config_port_stats()
Dsparx5_switchdev.c508 spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(enable), in sparx5_cpu_copy_ena()
Dsparx5_main.h653 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, in spx5_rmw() function