352 	spx5_rmw(0,  in sparx5_port_disable()
358 	spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS,  in sparx5_port_disable()
364 	spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1),  in sparx5_port_disable()
374 	spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |  in sparx5_port_disable()
386 	spx5_rmw(0,  in sparx5_port_disable()
422 	spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |  in sparx5_port_disable()
441 			spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0),  in sparx5_port_disable()
447 		spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0),  in sparx5_port_disable()
529 		spx5_rmw(BIT(inst),  in sparx5_port_mux_set()
536 			spx5_rmw(PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(1) |  in sparx5_port_mux_set()
647 	spx5_rmw(DSM_MAC_CFG_HDX_BACKPREASSURE_SET(conf->duplex == DUPLEX_HALF),  in sparx5_port_fc_setup()
653 	spx5_rmw(DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(fc_obey),  in sparx5_port_fc_setup()
659 	spx5_rmw(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(fc_obey),  in sparx5_port_fc_setup()
665 	spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop),  in sparx5_port_fc_setup()
750 	spx5_rmw(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(sgmii),  in sparx5_port_pcs_low_set()
775 	spx5_rmw(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(2) |  in sparx5_port_pcs_low_set()
808 		spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(1),  in sparx5_port_pcs_high_set()
849 		spx5_rmw(hsd ? 0 : bt_indx,  in sparx5_dev_switch()
854 		spx5_rmw(hsd ? 0 : bt_indx,  in sparx5_dev_switch()
859 		spx5_rmw(hsd ? 0 : bt_indx,  in sparx5_dev_switch()
882 	spx5_rmw(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(gig_mode) |  in sparx5_port_config_low_set()
897 	spx5_rmw(HSCH_PORT_MODE_AGE_DIS_SET(fdx == 0),  in sparx5_port_config_low_set()
909 	spx5_rmw(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(clk_spd) |  in sparx5_port_config_low_set()
953 		spx5_rmw(ASM_PORT_CFG_CSC_STAT_DIS_SET(high_speed_dev),  in sparx5_port_pcs_set()
959 		spx5_rmw(DSM_BUF_CFG_CSC_STAT_DIS_SET(high_speed_dev),  in sparx5_port_pcs_set()
992 	spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm),  in sparx5_port_config()
999 	spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1) |  in sparx5_port_config()
1044 	spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN),  in sparx5_port_init()
1057 	spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) |  in sparx5_port_init()
1075 	spx5_rmw(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(0),  in sparx5_port_init()
1087 			spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1),  in sparx5_port_init()
1096 		spx5_rmw(DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(0),  in sparx5_port_init()
1148 	spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(enable),  in sparx5_port_enable()
1180 	spx5_rmw(REW_TAG_CTRL_TAG_PCP_CFG_SET(mode) |  in sparx5_port_qos_pcp_rewr_set()
1201 			spx5_rmw(REW_PCP_MAP_DE1_PCP_DE1_SET(pcp),  in sparx5_port_qos_pcp_rewr_set()
1205 			spx5_rmw(REW_DEI_MAP_DE1_DEI_DE1_SET(dei),  in sparx5_port_qos_pcp_rewr_set()
1209 			spx5_rmw(REW_PCP_MAP_DE0_PCP_DE0_SET(pcp),  in sparx5_port_qos_pcp_rewr_set()
1213 			spx5_rmw(REW_DEI_MAP_DE0_DEI_DE0_SET(dei),  in sparx5_port_qos_pcp_rewr_set()
1231 	spx5_rmw(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(qos->qos_enable) |  in sparx5_port_qos_pcp_set()
1240 		spx5_rmw(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(pcp) |  in sparx5_port_qos_pcp_set()
1253 	spx5_rmw(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(mode),  in sparx5_port_qos_dscp_rewr_mode_set()
1272 	spx5_rmw(REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(rewr),  in sparx5_port_qos_dscp_rewr_set()
1281 		spx5_rmw(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(dscp),  in sparx5_port_qos_dscp_rewr_set()
1299 	spx5_rmw(ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(qos->qos_enable) |  in sparx5_port_qos_dscp_set()
1308 		spx5_rmw(ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(*(dscp + i)) |  in sparx5_port_qos_dscp_set()
1318 			spx5_rmw(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(1),  in sparx5_port_qos_dscp_set()
1333 	spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) |  in sparx5_port_qos_default_set()
1340 	spx5_rmw(ANA_CL_VLAN_CTRL_PORT_PCP_SET(0) |  in sparx5_port_qos_default_set()