Searched refs:reg_layout (Results 1 – 13 of 13) sorted by relevance
/linux-6.12.1/drivers/soundwire/ |
D | qcom.c | 182 const unsigned int *reg_layout; member 221 const unsigned int *reg_layout; member 240 .reg_layout = swrm_v1_3_reg_layout, 247 .reg_layout = swrm_v1_3_reg_layout, 255 .reg_layout = swrm_v1_3_reg_layout, 275 .reg_layout = swrm_v2_0_reg_layout, 359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail() 385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail() 410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done() 416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done() [all …]
|
/linux-6.12.1/drivers/tty/serial/8250/ |
D | 8250_dfl.c | 55 u64 fifo_len, clk_freq, reg_layout; in dfl_uart_get_params() local 86 ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); in dfl_uart_get_params() 90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params() 91 reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); in dfl_uart_get_params()
|
/linux-6.12.1/drivers/clk/renesas/ |
D | renesas-cpg-mssr.c | 155 enum clk_reg_layout reg_layout; member 211 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable() 233 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable() 261 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled() 300 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get() 903 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq() 934 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq() 943 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq() 1031 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init() 1081 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init() [all …]
|
D | renesas-cpg-mssr.h | 136 enum clk_reg_layout reg_layout; member
|
D | r7s9210-cpg-mssr.c | 217 .reg_layout = CLK_REG_LAYOUT_RZ_A,
|
D | r8a779f0-cpg-mssr.c | 237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
D | r8a779a0-cpg-mssr.c | 305 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
D | r8a779g0-cpg-mssr.c | 304 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
D | r8a779h0-cpg-mssr.c | 301 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
/linux-6.12.1/drivers/dma/ |
D | hisi_dma.c | 164 enum hisi_dma_reg_layout reg_layout; member 369 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_mask_irq() 385 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_unmask_irq() 638 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_init_hw_qp() 803 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_set_mode() 813 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) { in hisi_dma_init_hw() 851 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs() 862 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs() 928 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_create_debugfs() 952 enum hisi_dma_reg_layout reg_layout; in hisi_dma_probe() local [all …]
|
/linux-6.12.1/sound/soc/codecs/ |
D | lpass-wsa-macro.c | 403 const struct wsa_reg_layout *reg_layout; member 1181 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_set_prim_interpolator_rate() 1183 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_set_prim_interpolator_rate() 1185 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask); in wsa_macro_set_prim_interpolator_rate() 1226 wsa->reg_layout->rx_intx_2_sel_mask); in wsa_macro_set_mix_interpolator_rate() 1609 (comp * wsa->reg_layout->compander1_reg_offset); in wsa_macro_config_compander() 1655 u16 softclip_clk_reg = wsa->reg_layout->softclip0_reg_base + in wsa_macro_enable_softclip_clk() 1656 (path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_enable_softclip_clk() 1701 (softclip_path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_config_softclip() 1734 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_adie_lb() [all …]
|
/linux-6.12.1/drivers/clk/samsung/ |
D | clk.h | 293 enum exynos_cpuclk_layout reg_layout; member 305 .reg_layout = _layout, \
|
D | clk-cpu.c | 679 cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; in exynos_register_cpu_clock()
|