182 	const unsigned int *reg_layout;  member
221 	const unsigned int *reg_layout;  member
240 	.reg_layout = swrm_v1_3_reg_layout,
247 	.reg_layout = swrm_v1_3_reg_layout,
255 	.reg_layout = swrm_v1_3_reg_layout,
275 	.reg_layout = swrm_v2_0_reg_layout,
359 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in swrm_wait_for_rd_fifo_avail()
385 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in swrm_wait_for_wr_fifo_avail()
410 	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);  in swrm_wait_for_wr_fifo_done()
416 			ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);  in swrm_wait_for_wr_fifo_done()
454 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);  in qcom_swrm_cmd_fifo_wr_cmd()
494 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);  in qcom_swrm_cmd_fifo_rd_cmd()
502 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],  in qcom_swrm_cmd_fifo_rd_cmd()
514 						ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],  in qcom_swrm_cmd_fifo_rd_cmd()
674 	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],  in qcom_swrm_irq_handler()
714 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
719 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
727 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
735 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
744 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
757 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
767 						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_irq_handler()
781 					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],  in qcom_swrm_irq_handler()
798 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_irq_handler()
800 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],  in qcom_swrm_irq_handler()
815 		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],  in swrm_wait_for_frame_gen_enabled()
847 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],  in qcom_swrm_init()
884 	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],  in qcom_swrm_init()
889 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],  in qcom_swrm_init()
1504 	ctrl->reg_layout = data->reg_layout;
1701 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1707 					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1709 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1735 					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1737 		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],