| /linux-6.12.1/drivers/phy/ |
| D | phy-airoha-pcie.c | 83 #define airoha_phy_csr_2l_clear_bits(pcie_phy, reg, mask) \ argument
84 airoha_phy_clear_bits((pcie_phy)->csr_2l + (reg), (mask))
85 #define airoha_phy_csr_2l_set_bits(pcie_phy, reg, mask) \ argument
86 airoha_phy_set_bits((pcie_phy)->csr_2l + (reg), (mask))
87 #define airoha_phy_csr_2l_update_field(pcie_phy, reg, mask, val) \ argument
88 airoha_phy_update_field((pcie_phy)->csr_2l + (reg), (mask), (val))
89 #define airoha_phy_pma0_clear_bits(pcie_phy, reg, mask) \ argument
90 airoha_phy_clear_bits((pcie_phy)->pma0 + (reg), (mask))
91 #define airoha_phy_pma1_clear_bits(pcie_phy, reg, mask) \ argument
92 airoha_phy_clear_bits((pcie_phy)->pma1 + (reg), (mask))
[all …]
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| /linux-6.12.1/drivers/phy/mediatek/ |
| D | phy-mtk-pcie.c | 80 static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy, in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
89 addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG + in mtk_pcie_efuse_set_lane()
112 struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy); in mtk_pcie_phy_init() local
115 if (!pcie_phy->sw_efuse_en) in mtk_pcie_phy_init()
119 mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, in mtk_pcie_phy_init()
120 EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr); in mtk_pcie_phy_init()
122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init()
123 mtk_pcie_efuse_set_lane(pcie_phy, i); in mtk_pcie_phy_init()
133 static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy, in mtk_pcie_efuse_read_for_lane() argument
[all …]
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| /linux-6.12.1/arch/mips/pci/ |
| D | pci-mt7620.c | 128 static void pcie_phy(unsigned long addr, unsigned long val) in pcie_phy() function
224 pcie_phy(0x0, 0x80); in mt7620_pci_hw_init()
225 pcie_phy(0x1, 0x04); in mt7620_pci_hw_init()
228 pcie_phy(0x68, 0xB4); in mt7620_pci_hw_init()
|
| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | brcm,sr-pcie-phy.txt | 26 pcie_phy: phy@40000000 {
39 phys = <&pcie_phy 0>;
|
| D | rockchip-pcie-phy.txt | 28 pcie_phy: pcie-phy {
|
| /linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-pcie.dtsi | 37 phys = <&pcie_phy 8>;
47 pcie_phy: phy@0 { label
|
| /linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
| D | imx7d.dtsi | 144 clock-names = "pcie", "pcie_bus", "pcie_phy";
156 fsl,imx7d-pcie-phy = <&pcie_phy>;
163 pcie_phy: pcie-phy@306d0000 { label
|
| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3399-khadas-edge-v.dts | 23 &pcie_phy {
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| D | rk3399-khadas-edge-captain.dts | 23 &pcie_phy {
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| D | rk3399-roc-pc-mezzanine.dts | 59 &pcie_phy {
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| D | rk3399-sapphire-excavator.dts | 195 &pcie_phy {
|
| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8mm-verdin-yavia.dtsi | 107 &pcie_phy {
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| D | imx8mm-verdin-mallow.dtsi | 106 &pcie_phy {
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| D | imx8mm-verdin-dev.dtsi | 107 &pcie_phy {
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| D | imx8mp-verdin-mallow.dtsi | 167 &pcie_phy {
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| D | imx8mm-verdin-dahlia.dtsi | 124 &pcie_phy {
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| D | imx8mm-venice-gw71xx.dtsi | 105 &pcie_phy {
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| D | imx8mp-verdin-yavia.dtsi | 177 &pcie_phy {
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| D | imx8mp-venice-gw71xx.dtsi | 106 &pcie_phy {
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| D | imx8mm-iot-gateway.dts | 127 &pcie_phy {
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| D | imx8mp-verdin-dev.dtsi | 191 &pcie_phy {
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a-acelink-ew-7886cax.dts | 91 &pcie_phy {
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm5301x.dtsi | 82 clock-output-names = "lcpll0", "pcie_phy",
|
| /linux-6.12.1/arch/arm/boot/dts/qcom/ |
| D | qcom-sdx65.dtsi | 210 <&pcie_phy>,
343 phys = <&pcie_phy>;
352 pcie_phy: phy@1c06000 { label
|
| D | qcom-sdx55.dtsi | 377 phys = <&pcie_phy>;
436 phys = <&pcie_phy>;
444 pcie_phy: phy@1c06000 { label
|