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Searched refs:ivpu_dbg (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/accel/ivpu/
Divpu_fw.c111 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", in ivpu_fw_check_api()
191 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", in ivpu_fw_parse()
232 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", in ivpu_fw_parse()
234 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", in ivpu_fw_parse()
236 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", in ivpu_fw_parse()
420 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", in ivpu_fw_boot_params_print()
422 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", in ivpu_fw_boot_params_print()
424 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", in ivpu_fw_boot_params_print()
426 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", in ivpu_fw_boot_params_print()
428 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", in ivpu_fw_boot_params_print()
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Divpu_pm.c54 ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address); in ivpu_pm_prepare_warm_boot()
198 ivpu_dbg(vdev, PM, "Suspend..\n"); in ivpu_pm_suspend_cb()
214 ivpu_dbg(vdev, PM, "Suspend done.\n"); in ivpu_pm_suspend_cb()
225 ivpu_dbg(vdev, PM, "Resume..\n"); in ivpu_pm_resume_cb()
231 ivpu_dbg(vdev, PM, "Resume done.\n"); in ivpu_pm_resume_cb()
246 ivpu_dbg(vdev, PM, "Runtime suspend..\n"); in ivpu_pm_runtime_suspend_cb()
271 ivpu_dbg(vdev, PM, "Runtime suspend done.\n"); in ivpu_pm_runtime_suspend_cb()
282 ivpu_dbg(vdev, PM, "Runtime resume..\n"); in ivpu_pm_runtime_resume_cb()
288 ivpu_dbg(vdev, PM, "Runtime resume done.\n"); in ivpu_pm_runtime_resume_cb()
313 ivpu_dbg(vdev, PM, "Pre-reset..\n"); in ivpu_pm_reset_prepare_cb()
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Divpu_hw_reg_io.h54 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s started (expected 0x%x)\n", \
58 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s %s (reg val 0x%08x)\n", \
67 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s started (expected 0x%x)\n", \
71 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) Polling field %s %s (reg val 0x%08x)\n", \
82 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_rd32()
92 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_rd64()
100 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_wr32()
108 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_wr64()
119 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val); in ivpu_hw_reg_wr32_index()
Divpu_mmu.c313 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
317 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
321 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); in ivpu_mmu_config_check()
332 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
345 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
364 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", in ivpu_mmu_strtab_alloc()
383 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_cmdq_alloc()
402 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_evtq_alloc()
505 ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1); in ivpu_mmu_cmdq_cmd_write()
669 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]); in ivpu_mmu_strtab_link_cd()
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Divpu_drv.c74 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n", in ivpu_file_priv_get()
84 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id); in file_priv_unbind()
100 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n", in file_priv_release()
121 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n", in ivpu_file_priv_put()
267 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", in ivpu_open()
289 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", in ivpu_postclose()
340 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n"); in ivpu_wait_for_ready()
532 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
539 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
Divpu_fw_log.c43 ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", log->header_size); in fw_log_ptr()
47 ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", log->size); in fw_log_ptr()
54 ivpu_dbg(vdev, FW_BOOT, in fw_log_ptr()
Divpu_job.c160 ivpu_dbg(vdev, JOB, "DB %d registered to ctx %d\n", cmdq->db_id, file_priv->ctx.id); in ivpu_register_db()
217 ivpu_dbg(vdev, JOB, "Command queue %d destroyed\n", cmdq->db_id); in ivpu_cmdq_fini()
222 ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id); in ivpu_cmdq_fini()
352 ivpu_dbg(vdev, JOB, "Job queue full: ctx %d engine %d db %d head %d tail %d\n", in ivpu_cmdq_push_job()
427 ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d engine %d", in ivpu_job_destroy()
460 ivpu_dbg(vdev, JOB, "Job created: ctx %2d engine %d", file_priv->ctx.id, job->engine_idx); in ivpu_job_create()
499 ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d engine %d status 0x%x\n", in ivpu_job_signal_and_destroy()
548 ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n", in ivpu_job_submit()
569 ivpu_dbg(vdev, JOB, "Job submitted: id %3u ctx %2d engine %d prio %d addr 0x%llx next %d\n", in ivpu_job_submit()
711 ivpu_dbg(vdev, JOB, "Submit ioctl: ctx %u buf_count %u\n", in ivpu_submit_ioctl()
Divpu_hw_btrs.c150 ivpu_dbg(vdev, MISC, "Fuse: %d tiles enabled. Tile number %d disabled\n", in read_tile_config_fuse()
153 ivpu_dbg(vdev, MISC, "Fuse: All %d tiles enabled\n", BTRS_LNL_TILE_MAX_NUM); in read_tile_config_fuse()
343 ivpu_dbg(vdev, PM, "Skipping workpoint request\n"); in ivpu_hw_btrs_wp_drive()
349 ivpu_dbg(vdev, PM, "PLL workpoint request: %u Hz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", in ivpu_hw_btrs_wp_drive()
551 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_btrs_ats_print_lnl()
601 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", in ivpu_hw_btrs_irq_handler_mtl()
647 ivpu_dbg(vdev, IRQ, "Survivability IRQ\n"); in ivpu_hw_btrs_irq_handler_lnl()
653 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(VPU_HW_BTRS_LNL_PLL_FREQ)); in ivpu_hw_btrs_irq_handler_lnl()
Divpu_drv.h89 #define ivpu_dbg(vdev, type, fmt, args...) do { \ macro
98 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
Divpu_ipc.c29 ivpu_dbg(vdev, IPC, in ivpu_ipc_msg_dump()
40 ivpu_dbg(vdev, JSM, in ivpu_jsm_msg_dump()
281 ivpu_dbg(vdev, IPC, "IPC resp result error: %d\n", rx_msg->jsm_msg->result); in ivpu_ipc_receive()
439 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); in ivpu_ipc_irq_handler()
Divpu_mmu_context.c352 ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr); in ivpu_mmu_context_split_64k_page()
376 ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_set_pages_ro()
445 ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_map_sgt()
485 ivpu_dbg(vdev, MMU_MAP, "Unmap ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_unmap_sgt()
Divpu_hw_ip.c822 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in soc_cpu_boot_37xx()
903 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in soc_cpu_boot_40xx()
1067 ivpu_dbg(vdev, IRQ, "NOC Firewall interrupt detected, counter %d\n", in irq_noc_firewall_handler()
1088 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_ip_irq_handler_37xx()
1122 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_ip_irq_handler_40xx()
Divpu_hw.c52 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in platform_init()
Divpu_gem.c27 ivpu_dbg(vdev, BO, in ivpu_dbg_bo()