invalidate (reference) in projects: linux-6.12.1

Searched refs:invalidate (Results 1 – 25 of 143) sorted by relevance

/linux-6.12.1/arch/arm/mm/
D	cache-v6.S	43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 152 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB [all …]
D	cache-fa.S	45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 132 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB [all …]
D	proc-arm926.S	72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 137 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm925.S	112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 169 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 173 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-mohawk.S	65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 143 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 145 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 146 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm922.S	82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 165 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 203 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 223 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	cache-v4wt.S	`49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 72 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 91 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 93 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 165 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
D	proc-arm920.S	80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 201 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 221 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 226 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-fa526.S	61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM [all …]
D	proc-arm1022.S	88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 248 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
D	proc-arm1026.S	88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate 150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 220 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 273 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
D	proc-arm946.S	90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm1020e.S	88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 226 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 249 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 279 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
D	tlb-v7.S	`50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA`
D	tlb-v6.S	`49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA`
D	proc-arm1020.S	88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 181 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 231 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 254 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 289 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
D	proc-feroceon.S	98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 185 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 188 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 189 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-xsc3.S	69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 206 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 255 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line [all …]
D	cache-v4wb.S	`59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 200 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
D	cache-v7.S	86 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 87 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 166 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way 201 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 202 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 217 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 218 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 306 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 311 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 312 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB [all …]
D	tlb-v4wb.S	`39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry`
D	tlb-v4wbi.S	`41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry`
D	proc-sa1100.S	`76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 194 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4`
D	proc-sa110.S	`68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4`
D	proc-xscale.S	151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 313 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 340 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 375 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 457 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 529 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 530 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB [all …]

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