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Searched refs:hw_ctl (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_wb.c225 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_wb_setup_ctl()
229 (phys_enc->hw_ctl && in dpu_encoder_phys_wb_setup_ctl()
230 phys_enc->hw_ctl->ops.setup_intf_cfg)) { in dpu_encoder_phys_wb_setup_ctl()
255 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
256 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_wb_setup_ctl()
263 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
274 struct dpu_hw_ctl *hw_ctl; in _dpu_encoder_phys_wb_update_flush() local
285 hw_ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_wb_update_flush()
291 if (!hw_ctl) { in _dpu_encoder_phys_wb_update_flush()
296 if (hw_ctl->ops.update_pending_flush_wb) in _dpu_encoder_phys_wb_update_flush()
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Ddpu_encoder_phys_vid.c263 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { in dpu_encoder_phys_vid_setup_timing_engine()
312 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
331 struct dpu_hw_ctl *hw_ctl; in dpu_encoder_phys_vid_vblank_irq() local
335 hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_vblank_irq()
349 if (hw_ctl->ops.get_flush_register) in dpu_encoder_phys_vid_vblank_irq()
350 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); in dpu_encoder_phys_vid_vblank_irq()
352 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) in dpu_encoder_phys_vid_vblank_irq()
445 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_enable()
527 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; in dpu_encoder_phys_vid_wait_for_commit_done() local
530 if (!hw_ctl) in dpu_encoder_phys_vid_wait_for_commit_done()
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Ddpu_encoder.c633 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_assign_crtc_resources() local
643 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_assign_crtc_resources()
654 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); in dpu_encoder_assign_crtc_resources()
1135 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set() local
1165 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); in dpu_encoder_virt_atomic_mode_set()
1201 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL; in dpu_encoder_virt_atomic_mode_set()
1202 if (!phys->hw_ctl) { in dpu_encoder_virt_atomic_mode_set()
1546 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1594 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_trigger_start()
1636 ctl = phys_enc->hw_ctl; in dpu_encoder_helper_hw_reset()
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Ddpu_encoder_phys_cmd.c57 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
150 phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; in dpu_encoder_phys_cmd_atomic_mode_set()
195 phys_enc->hw_ctl->idx - CTL_0, in _dpu_encoder_phys_cmd_handle_ppdone_timeout()
419 if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { in _dpu_encoder_phys_cmd_pingpong_config()
456 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_enable_helper()
564 ctl = phys_enc->hw_ctl; in dpu_encoder_phys_cmd_disable()
680 if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl)) in dpu_encoder_phys_cmd_wait_for_commit_done()
Ddpu_encoder_phys.h180 struct dpu_hw_ctl *hw_ctl; member