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/linux-6.12.1/arch/arm/mm/
Dproc-arm940.S57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
197 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
247 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
285 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
288 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
289 mcr p15, 0, r0, c6, c4, 0
290 mcr p15, 0, r0, c6, c5, 0
291 mcr p15, 0, r0, c6, c6, 0
292 mcr p15, 0, r0, c6, c7, 0
[all …]
Dproc-arm740.S76 mcr p15, 0, r0, c6, c3 @ disable area 3~7
77 mcr p15, 0, r0, c6, c4
78 mcr p15, 0, r0, c6, c5
79 mcr p15, 0, r0, c6, c6
80 mcr p15, 0, r0, c6, c7
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
93 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
106 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
Dproc-arm946.S64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
246 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
290 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
338 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
341 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
342 mcr p15, 0, r0, c6, c4, 0
343 mcr p15, 0, r0, c6, c5, 0
[all …]
Dpmsa-v7.c38 #define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
39 #define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
40 #define DRSR __ACCESS_CP15(c6, 0, c1, 2)
41 #define IRSR __ACCESS_CP15(c6, 0, c1, 3)
42 #define DRACR __ACCESS_CP15(c6, 0, c1, 4)
43 #define IRACR __ACCESS_CP15(c6, 0, c1, 5)
44 #define RNGNR __ACCESS_CP15(c6, 0, c2, 0)
Dcache-v4wt.S72 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
91 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
165 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Dtlb-v4wb.S42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dtlb-v4wbi.S42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dproc-arm925.S169 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
301 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
401 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
Dproc-arm926.S135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
264 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
365 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
Dcache-v4wb.S119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
200 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
Dpmsa-v8.c21 #define PRSEL __ACCESS_CP15(c6, 0, c2, 1)
22 #define PRBAR __ACCESS_CP15(c6, 0, c3, 0)
23 #define PRLAR __ACCESS_CP15(c6, 0, c3, 1)
Dpabort-v7.S19 mrc p15, 0, r0, c6, c0, 2 @ get IFAR
Dproc-xscale.S243 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
313 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
340 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
375 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
515 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
531 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
Dabort-ev7.S19 mrc p15, 0, r0, c6, c0, 0 @ get FAR
Dabort-ev4.S21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
Dabort-ev4t.S22 mrc p15, 0, r0, c6, c0, 0 @ get FAR
Dabort-ev5t.S22 mrc p15, 0, r0, c6, c0, 0 @ get FAR
Dabort-ev5tj.S22 mrc p15, 0, r0, c6, c0, 0 @ get FAR
Dabort-ev6.S23 mrc p15, 0, r0, c6, c0, 0 @ get FAR
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s520 cxsout $c6
541 cxor $c6 $c0
542 cenc $c6 $c6
543 cxsout $c6
549 cmov $c2 $c6
550 cxsin $c6
551 cdec $c0 $c6
559 cxor $c6 $c0
560 cenc $c6 $c6
561 cxsout $c6
[all …]
/linux-6.12.1/arch/arm/kernel/
Dhead-nommu.S219 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
224 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
225 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
226 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
337 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
350 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
364 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
365 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
388 AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2
[all …]
/linux-6.12.1/arch/arm/include/asm/hardware/
Dcp14.h48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
63 #define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
79 #define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
95 #define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
111 #define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
128 #define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
168 #define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
184 #define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
200 #define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6)
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Daes-tab-4k.S33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
132 .long R(73, b4, b4, c7), R(97, c6, c6, 51)
156 .long R(84, 42, 42, c6), R(d0, 68, 68, b8)
175 .long R(8d, 46, 97, a3), R(6b, d3, f9, c6)
232 .long R(8b, 43, 29, 76), R(cb, 23, c6, dc)
235 .long R(13, 97, 22, 40), R(84, c6, 11, 20)
263 .long R(c6, a5, 94, 30), R(35, a2, 66, c0)
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dipq9574-rdp449.dts15 compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";

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