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Searched refs:bMaskByte0 (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/drivers/staging/rtl8723bs/hal/
Dodm_DIG.c21 …PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /* 0xe28[7:0]= 0xff th_… in odm_NHMCounterStatisticsInit()
44 pDM_Odm->NHM_cnt_0 = (u8)(value32 & bMaskByte0); in odm_GetNHMCounterStatistics()
137 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc); in odm_SearchPwdBLowerBound()
160 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc); in odm_SearchPwdBLowerBound()
242 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, 0x7f); in odm_Adaptivity()
280 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc); in odm_Adaptivity()
669 pDM_Odm->Adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0 in odm_FalseAlarmCounterStatistics()
Drtl8723b_phycfg.c471 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); in PHY_SetTxPowerIndex()
484 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); in PHY_SetTxPowerIndex()
497 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); in PHY_SetTxPowerIndex()
510 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); in PHY_SetTxPowerIndex()
DHalPhyRf_8723B.c1326 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0); in phy_IQCalibrate_8723B()
1327 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0); in phy_IQCalibrate_8723B()
1495 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50); in phy_IQCalibrate_8723B()
1496 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50); in phy_IQCalibrate_8723B()
1498 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50); in phy_IQCalibrate_8723B()
1499 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58); in phy_IQCalibrate_8723B()
1627 …path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? RF_PATH_A : RF_P… in PHY_IQCalibrate_8723B()
/linux-6.12.1/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h217 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ macro
/linux-6.12.1/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h726 #define bMaskByte0 0xff macro
Dr8192E_phy.c922 BitMask = bMaskByte0; in rtl92e_init_gain()
/linux-6.12.1/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h968 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ macro