Searched refs:TEGRA234_CLK_PLLP_OUT0 (Results 1 – 4 of 4) sorted by relevance
183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;2791 <&bpmp TEGRA234_CLK_PLLP_OUT0>;2793 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;2810 <&bpmp TEGRA234_CLK_PLLP_OUT0>;2812 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;2829 <&bpmp TEGRA234_CLK_PLLP_OUT0>;2831 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;2848 <&bpmp TEGRA234_CLK_PLLP_OUT0>;2850 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;2867 <&bpmp TEGRA234_CLK_PLLP_OUT0>;[all …]
56 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
97 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
205 #define TEGRA234_CLK_PLLP_OUT0 102U macro