Lines Matching refs:TEGRA234_CLK_PLLP_OUT0

183 				assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2791 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2793 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2810 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2812 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2829 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2831 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2848 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2850 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2867 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2869 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2893 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2895 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2911 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2932 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3861 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3864 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3880 				 <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3883 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3900 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;