Searched refs:TEGRA234_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
209 #define TEGRA234_CLK_PLLA_OUT0 104U macro
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;235 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;271 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;307 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;943 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;977 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;1011 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;1045 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;[all …]