Lines Matching refs:TEGRA234_CLK_PLLA_OUT0

199 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
235 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
271 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
307 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
343 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
379 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
943 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
977 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1011 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1045 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1079 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1113 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5736 			 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
5739 				  <&bpmp TEGRA234_CLK_PLLA_OUT0>,
5743 					 <&bpmp TEGRA234_CLK_PLLA_OUT0>;