Searched refs:RF90_PATH_D (Results 1 – 25 of 25) sorted by relevance
160 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in rtl8723_phy_init_bb_rf_reg_def()165 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in rtl8723_phy_init_bb_rf_reg_def()181 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in rtl8723_phy_init_bb_rf_reg_def()186 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl8723_phy_init_bb_rf_reg_def()197 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in rtl8723_phy_init_bb_rf_reg_def()202 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in rtl8723_phy_init_bb_rf_reg_def()207 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in rtl8723_phy_init_bb_rf_reg_def()212 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in rtl8723_phy_init_bb_rf_reg_def()217 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in rtl8723_phy_init_bb_rf_reg_def()222 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in rtl8723_phy_init_bb_rf_reg_def()[all …]
149 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in rtl92d_phy_init_bb_rf_register_definition()158 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in rtl92d_phy_init_bb_rf_register_definition()184 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in rtl92d_phy_init_bb_rf_register_definition()194 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in rtl92d_phy_init_bb_rf_register_definition()213 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in rtl92d_phy_init_bb_rf_register_definition()219 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in rtl92d_phy_init_bb_rf_register_definition()225 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in rtl92d_phy_init_bb_rf_register_definition()231 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in rtl92d_phy_init_bb_rf_register_definition()237 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in rtl92d_phy_init_bb_rf_register_definition()243 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in rtl92d_phy_init_bb_rf_register_definition()[all …]
73 case RF90_PATH_D: in _rtl92ee_phy_rf6052_config_parafile()103 case RF90_PATH_D: in _rtl92ee_phy_rf6052_config_parafile()114 case RF90_PATH_D: in _rtl92ee_phy_rf6052_config_parafile()
390 if (path > RF90_PATH_D) { in _rtl92ee_phy_set_txpower_by_rate_base()430 if (path > RF90_PATH_D) { in _rtl92ee_phy_get_txpower_by_rate_base()996 case RF90_PATH_D: in rtl92ee_phy_config_rf_with_headerfile()
672 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92s_phy_init_register_definition()678 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92s_phy_init_register_definition()684 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()690 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()699 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = in _rtl92s_phy_init_register_definition()706 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92s_phy_init_register_definition()712 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()718 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()724 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()730 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92s_phy_init_register_definition()[all …]
421 case RF90_PATH_D: in rtl92s_phy_rf6052_config()453 case RF90_PATH_D: in rtl92s_phy_rf6052_config()465 case RF90_PATH_D: in rtl92s_phy_rf6052_config()
156 case RF90_PATH_D: in rtl92d_phy_rf6052_config()191 case RF90_PATH_D: in rtl92d_phy_rf6052_config()201 case RF90_PATH_D: in rtl92d_phy_rf6052_config()
507 case RF90_PATH_D: in rtl92d_phy_config_rf_with_headerfile()
168 case RF90_PATH_D: in rtl92du_phy_rf6052_config()204 case RF90_PATH_D: in rtl92du_phy_rf6052_config()215 case RF90_PATH_D: in rtl92du_phy_rf6052_config()
499 case RF90_PATH_D: in rtl92du_phy_config_rf_with_headerfile()
403 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()408 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()424 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()429 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()440 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()445 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()450 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()455 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()460 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()465 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()[all …]
429 case RF90_PATH_D: in _rtl88e_phy_rf6052_config_parafile()459 case RF90_PATH_D: in _rtl88e_phy_rf6052_config_parafile()470 case RF90_PATH_D: in _rtl88e_phy_rf6052_config_parafile()
769 case RF90_PATH_D: in rtl88e_phy_config_rf_with_headerfile()814 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()819 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()835 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()840 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()854 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()860 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()865 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()870 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()875 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl88e_phy_init_bb_rf_register_definition()[all …]
396 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()418 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()428 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()
254 case RF90_PATH_D: in rtl92cu_phy_config_rf_with_headerfile()
425 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()455 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()466 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()
277 case RF90_PATH_D: in rtl92c_phy_config_rf_with_headerfile()
433 case RF90_PATH_D: in _rtl8723be_phy_rf6052_config_parafile()463 case RF90_PATH_D: in _rtl8723be_phy_rf6052_config_parafile()474 case RF90_PATH_D: in _rtl8723be_phy_rf6052_config_parafile()
285 if (path > RF90_PATH_D) { in _rtl8723be_phy_set_txpower_by_rate_base()327 if (path > RF90_PATH_D) { in _rtl8723be_phy_get_txpower_by_rate_base()764 case RF90_PATH_D: in rtl8723be_phy_config_rf_with_headerfile()
434 case RF90_PATH_D: in _rtl8723e_phy_rf6052_config_parafile()465 case RF90_PATH_D: in _rtl8723e_phy_rf6052_config_parafile()476 case RF90_PATH_D: in _rtl8723e_phy_rf6052_config_parafile()
517 case RF90_PATH_D: in rtl8723e_phy_config_rf_with_headerfile()
426 case RF90_PATH_D: in _rtl8821ae_phy_rf6052_config_parafile()
907 if (path > RF90_PATH_D) { in _rtl8821ae_phy_set_txpower_by_rate_base()976 if (path > RF90_PATH_D) { in _rtl8821ae_phy_get_txpower_by_rate_base()2069 case RF90_PATH_D: in rtl8812ae_phy_config_rf_with_headerfile()2096 case RF90_PATH_D: in rtl8821ae_phy_config_rf_with_headerfile()
18 #define BTC_RF_D RF90_PATH_D
298 RF90_PATH_D = 3, enumerator