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Searched refs:REG_WAIT (Results 1 – 25 of 65) sorted by relevance

123

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
Ddcn302_hwseq.c60 REG_WAIT(DOMAIN1_PG_STATUS, in dcn302_dpp_pg_control()
68 REG_WAIT(DOMAIN3_PG_STATUS, in dcn302_dpp_pg_control()
76 REG_WAIT(DOMAIN5_PG_STATUS, in dcn302_dpp_pg_control()
84 REG_WAIT(DOMAIN7_PG_STATUS, in dcn302_dpp_pg_control()
92 REG_WAIT(DOMAIN9_PG_STATUS, in dcn302_dpp_pg_control()
117 REG_WAIT(DOMAIN0_PG_STATUS, in dcn302_hubp_pg_control()
125 REG_WAIT(DOMAIN2_PG_STATUS, in dcn302_hubp_pg_control()
133 REG_WAIT(DOMAIN4_PG_STATUS, in dcn302_hubp_pg_control()
141 REG_WAIT(DOMAIN6_PG_STATUS, in dcn302_hubp_pg_control()
149 REG_WAIT(DOMAIN8_PG_STATUS, in dcn302_hubp_pg_control()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c91 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_dmcu_load_iram()
115 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_get_dmcu_psr_state()
139 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
233 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
310 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
341 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
363 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
376 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
413 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
431 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
[all …]
Ddce_abm.c66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
106 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
134 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
206 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
Ddce_aux.c146 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
157 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
221 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
350 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/pg/dcn35/
Ddcn35_pg_cntl.c112 REG_WAIT(DOMAIN16_PG_STATUS, in pg_cntl35_dsc_pg_control()
120 REG_WAIT(DOMAIN17_PG_STATUS, in pg_cntl35_dsc_pg_control()
128 REG_WAIT(DOMAIN18_PG_STATUS, in pg_cntl35_dsc_pg_control()
136 REG_WAIT(DOMAIN19_PG_STATUS, in pg_cntl35_dsc_pg_control()
216 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hubp_dpp_pg_control()
221 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hubp_dpp_pg_control()
226 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hubp_dpp_pg_control()
231 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hubp_dpp_pg_control()
290 REG_WAIT(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_hpo_pg_control()
338 REG_WAIT(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in pg_cntl35_io_clk_pg_control()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn32/
Ddcn32_dio_stream_encoder.c299 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
314 REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
323 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc32_stream_encoder_dp_unblank()
327 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc32_stream_encoder_dp_unblank()
404 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc32_reset_fifo()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
Ddcn31_hpo_dp_stream_encoder.c73 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
81 REG_WAIT(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
107 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
112 REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */ in dcn31_hpo_dp_stream_enc_dp_unblank()
121 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
126 REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
153 REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_dp_blank()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_apg.c54 REG_WAIT(APG_CONTROL, in apg31_enable()
58 REG_WAIT(APG_CONTROL, in apg31_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
Ddcn31_hwseq.c306 REG_WAIT(DOMAIN16_PG_STATUS, in dcn31_dsc_pg_control()
314 REG_WAIT(DOMAIN17_PG_STATUS, in dcn31_dsc_pg_control()
322 REG_WAIT(DOMAIN18_PG_STATUS, in dcn31_dsc_pg_control()
458 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
462 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
466 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
470 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); in dcn31_hubp_pg_control()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn20/
Ddcn20_optc.c277 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
324 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_align_vblanks()
351 REG_WAIT(OTG_CONTROL, in optc2_align_vblanks()
392 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_triplebuffer_lock()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn32/
Ddcn32_optc.c128 REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING, 0, 2, 50000); in optc32_wait_odm_doublebuffer_pending_clear()
195 REG_WAIT(OTG_CLOCK_CONTROL, in optc32_disable_crtc()
210 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc32_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn30/
Ddcn30_optc.c58 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_triplebuffer_lock()
128 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc3_lock()
298 …REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdat… in optc3_wait_drr_doublebuffer_pending_clear()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn314/
Ddcn314_optc.c145 REG_WAIT(OTG_CLOCK_CONTROL, in optc314_disable_crtc()
160 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc314_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/
Ddcn31_hubbub.c118 REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1000, 30); in dcn31_wait_for_det_apply()
121 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1000, 30); in dcn31_wait_for_det_apply()
124 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1000, 30); in dcn31_wait_for_det_apply()
127 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1000, 30); in dcn31_wait_for_det_apply()
141 REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); in dcn31_program_compbuf_size()
142 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); in dcn31_program_compbuf_size()
143 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); in dcn31_program_compbuf_size()
144 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); in dcn31_program_compbuf_size()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
Ddcn314_hwseq.c225 REG_WAIT(DOMAIN16_PG_STATUS, in dcn314_dsc_pg_control()
233 REG_WAIT(DOMAIN17_PG_STATUS, in dcn314_dsc_pg_control()
241 REG_WAIT(DOMAIN18_PG_STATUS, in dcn314_dsc_pg_control()
249 REG_WAIT(DOMAIN19_PG_STATUS, in dcn314_dsc_pg_control()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn31/
Ddcn31_optc.c145 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_disable_crtc()
168 REG_WAIT(OTG_CLOCK_CONTROL, in optc31_immediate_disable_crtc()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
Ddcn401_hubbub.c1158 REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); in dcn401_program_compbuf_segments()
1159 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); in dcn401_program_compbuf_segments()
1160 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); in dcn401_program_compbuf_segments()
1161 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); in dcn401_program_compbuf_segments()
1179 …REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100000); /* 1 vupdate at 10… in dcn401_wait_for_det_update()
1182 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100000); in dcn401_wait_for_det_update()
1185 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100000); in dcn401_wait_for_det_update()
1188 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100000); in dcn401_wait_for_det_update()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_stream_encoder.c80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_update_generic_info_packet()
653 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in enc1_stream_encoder_set_throttled_vcp_size()
796 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
809 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_stream_encoder_send_immediate_sdp_message()
852 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
943 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/
Ddcn35_hubbub.c81 REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); in dcn35_program_compbuf_size()
82 REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); in dcn35_program_compbuf_size()
83 REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); in dcn35_program_compbuf_size()
84 REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); in dcn35_program_compbuf_size()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.c492 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
500 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
571 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
681 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc1_lock()
839 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
845 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn401/
Ddcn401_dio_stream_encoder.c324 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc401_stream_encoder_dp_unblank()
350 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); in enc401_stream_encoder_dp_unblank()
354 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000); in enc401_stream_encoder_dp_unblank()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn35/
Ddcn35_optc.c162 REG_WAIT(OTG_CLOCK_CONTROL, in optc35_disable_crtc()
178 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); in optc35_phantom_crtc_post_enable()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn35/
Ddcn35_dio_stream_encoder.c331 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc35_stream_encoder_dp_unblank()
389 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc35_reset_fifo()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn314/
Ddcn314_dio_stream_encoder.c62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc314_reset_fifo()
342 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); in enc314_stream_encoder_dp_unblank()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c182 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); in dcn20_update_clocks_update_dentist()
209 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); in dcn20_update_clocks_update_dentist()
212 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); in dcn20_update_clocks_update_dentist()

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