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Searched refs:REGV_WR32 (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/accel/ivpu/
Divpu_hw_ip.c82 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
240 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val); in idle_gen_drive_37xx()
252 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in idle_gen_drive_40xx()
285 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val); in pwr_island_delay_set_50xx()
289 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val); in pwr_island_delay_set_50xx()
301 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_37xx()
313 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_40xx()
328 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_37xx()
343 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_40xx()
379 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_37xx()
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Divpu_mmu.c439 REGV_WR32(IVPU_MMU_REG_CR0, val); in ivpu_mmu_reg_write_cr0()
446 REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val); in ivpu_mmu_reg_write_irq_ctrl()
524 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod); in ivpu_mmu_cmdq_sync()
590 REGV_WR32(IVPU_MMU_REG_CR1, val); in ivpu_mmu_reset()
593 REGV_WR32(IVPU_MMU_REG_STRTAB_BASE_CFG, mmu->strtab.base_cfg); in ivpu_mmu_reset()
596 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, 0); in ivpu_mmu_reset()
597 REGV_WR32(IVPU_MMU_REG_CMDQ_CONS, 0); in ivpu_mmu_reset()
617 REGV_WR32(IVPU_MMU_REG_EVTQ_PROD_SEC, 0); in ivpu_mmu_reset()
618 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, 0); in ivpu_mmu_reset()
917 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons); in ivpu_mmu_irq_evtq_handler()
[all …]
Divpu_hw_reg_io.h27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) macro