Searched refs:REGV_RD32 (Results 1 – 3 of 3) sorted by relevance
87 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx()97 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx()115 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_37xx()125 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_40xx()143 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_37xx()153 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_40xx()171 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_37xx()182 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_40xx()233 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN); in idle_gen_drive_37xx()245 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); in idle_gen_drive_40xx()[all …]
311 val = REGV_RD32(IVPU_MMU_REG_IDR0); in ivpu_mmu_config_check()315 val = REGV_RD32(IVPU_MMU_REG_IDR1); in ivpu_mmu_config_check()319 val = REGV_RD32(IVPU_MMU_REG_IDR3); in ivpu_mmu_config_check()330 val = REGV_RD32(IVPU_MMU_REG_IDR5); in ivpu_mmu_config_check()530 val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS); in ivpu_mmu_cmdq_sync()892 evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC); in ivpu_mmu_get_event()938 gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR); in ivpu_mmu_irq_gerr_handler()939 gerrorn_val = REGV_RD32(IVPU_MMU_REG_GERRORN); in ivpu_mmu_irq_gerr_handler()
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) macro