87 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);  in host_ss_noc_qreqn_check_37xx()
97 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in host_ss_noc_qreqn_check_40xx()
115 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN);  in host_ss_noc_qacceptn_check_37xx()
125 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN);  in host_ss_noc_qacceptn_check_40xx()
143 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY);  in host_ss_noc_qdeny_check_37xx()
153 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY);  in host_ss_noc_qdeny_check_40xx()
171 	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);  in top_noc_qrenqn_check_37xx()
182 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in top_noc_qrenqn_check_40xx()
233 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN);  in idle_gen_drive_37xx()
245 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN);  in idle_gen_drive_40xx()
283 	val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);  in pwr_island_delay_set_50xx()
287 	val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);  in pwr_island_delay_set_50xx()
294 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);  in pwr_island_trickle_drive_37xx()
306 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0);  in pwr_island_trickle_drive_40xx()
321 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);  in pwr_island_drive_37xx()
336 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);  in pwr_island_drive_40xx()
372 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0);  in pwr_island_isolation_drive_37xx()
384 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0);  in pwr_island_isolation_drive_40xx()
409 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET);  in host_ss_clk_drive_37xx()
426 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN);  in host_ss_clk_drive_40xx()
456 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET);  in host_ss_rst_drive_37xx()
473 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN);  in host_ss_rst_drive_40xx()
503 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN);  in host_ss_noc_qreqn_top_socmmio_drive_37xx()
514 	u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN);  in host_ss_noc_qreqn_top_socmmio_drive_40xx()
552 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN);  in top_noc_qreqn_drive_40xx()
567 	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN);  in top_noc_qreqn_drive_37xx()
595 	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN);  in top_noc_qacceptn_check_37xx()
606 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN);  in top_noc_qacceptn_check_40xx()
625 	u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY);  in top_noc_qdeny_check_37xx()
636 	u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY);  in top_noc_qdeny_check_40xx()
679 	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE);  in dpu_active_drive_37xx()
730 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES);  in ivpu_hw_ip_snoop_disable_37xx()
745 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES);  in ivpu_hw_ip_snoop_disable_40xx()
768 	u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV);  in ivpu_hw_ip_tbu_mmu_enable_37xx()
780 	u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV);  in ivpu_hw_ip_tbu_mmu_enable_40xx()
804 	val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC);  in soc_cpu_boot_37xx()
830 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN);  in cpu_noc_qacceptn_check_40xx()
840 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY);  in cpu_noc_qdeny_check_40xx()
850 	u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN);  in cpu_noc_top_mmio_drive_40xx()
899 	val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO);  in soc_cpu_boot_40xx()
930 	val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG);  in wdt_disable_37xx()
945 	val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG);  in wdt_disable_40xx()
1004 	u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;  in diagnose_failure_37xx()
1021 	u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;  in diagnose_failure_40xx()
1074 	u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX;  in ivpu_hw_ip_irq_handler_37xx()
1108 	u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX;  in ivpu_hw_ip_irq_handler_40xx()
1166 		return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM);  in ivpu_hw_ip_ipc_rx_addr_get()
1168 		return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM);  in ivpu_hw_ip_ipc_rx_addr_get()