| /linux-6.12.1/drivers/clk/stm32/ |
| D | clk-stm32mp1.c | 1383 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1887 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1888 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1889 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1890 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1891 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1892 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1893 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1894 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1895 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/gemini/ |
| D | gemini.dtsi | 163 clock-names = "PCLK";
187 clock-names = "PCLK", "EXTCLK";
197 clock-names = "PCLK", "EXTCLK";
284 clock-names = "PCLK", "PCICLK";
362 clock-names = "PCLK";
373 clock-names = "PCLK";
391 clock-names = "PCLK";
404 clock-names = "PCLK";
435 clock-names = "PCLK", "TVE";
447 clock-names = "PCLK";
[all …]
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| /linux-6.12.1/sound/soc/meson/ |
| D | aiu.c | 86 return clk_prepare_enable(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_probe()
93 clk_disable_unprepare(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_remove()
200 [PCLK] = "i2s_pclk",
207 [PCLK] = "spdif_pclk",
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| D | aiu.h | 18 PCLK = 0, enumerator
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| D | aiu-fifo-i2s.c | 169 fifo->pclk = aiu->i2s.clks[PCLK].clk; in aiu_fifo_i2s_dai_probe()
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| D | aiu-fifo-spdif.c | 184 fifo->pclk = aiu->spdif.clks[PCLK].clk; in aiu_fifo_spdif_dai_probe()
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| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | faraday,fttmr010.txt | 23 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
37 clock-names = "EXTCLK", "PCLK";
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| /linux-6.12.1/Documentation/admin-guide/media/ |
| D | mgb4.rst | 142 Width of the HSYNC signal in PCLK clock ticks.
148 Width of the VSYNC signal in PCLK clock ticks.
154 Number of PCLK pulses between deassertion of the HSYNC signal and the first
161 Number of PCLK pulses between the end of the last valid pixel in the video
183 derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
184 oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to
273 Number of PCLK pulses between deassertion of the HSYNC signal and the first
277 Number of PCLK pulses between the end of the last valid pixel in the video
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| /linux-6.12.1/arch/arm/boot/dts/moxa/ |
| D | moxart.dtsi | 65 clock-names = "PCLK";
93 clock-names = "PCLK";
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 28 #define PCLK 9 macro
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
318 ALIAS(PCLK, NULL, "pclk"),
319 ALIAS(PCLK, NULL, "clk_uart_baud2"),
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | st,nomadik.txt | 36 lines from the PCLK clock tree.
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| /linux-6.12.1/Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 34 * PCLK: Pixel Clock
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| /linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
| D | am437x-sbc-t43.dts | 61 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
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| D | am437x-sk-evm.dts | 373 AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
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| D | am43x-epos-evm.dts | 434 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
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| D | am437x-gp-evm.dts | 294 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
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| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | ste-nomadik-stn8815.dtsi | 232 /* The PCLK domain uses HCLK right off */
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| /linux-6.12.1/arch/arm/boot/dts/aspeed/ |
| D | aspeed-g4.dtsi | 294 clock-names = "PCLK";
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| D | aspeed-g6.dtsi | 511 clock-names = "PCLK";
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| D | aspeed-g5.dtsi | 378 clock-names = "PCLK";
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| /linux-6.12.1/Documentation/fb/ |
| D | matroxfb.rst | 143 transaction terminate with success or retry in 32 PCLK).
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| /linux-6.12.1/Documentation/networking/device_drivers/hamradio/ |
| D | z8530drv.rst | 109 pclock - the clock at the PCLK pin of the Z8530 (option, 4915200 is
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| /linux-6.12.1/drivers/watchdog/ |
| D | Kconfig | 557 The driver is limited by the speed of the system's PCLK
558 signal, so with reasonably fast systems (PCLK around 50-66MHz)
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