Home
last modified time | relevance | path

Searched refs:L2 (Results 1 – 25 of 300) sorted by relevance

12345678910>>...12

/linux-6.12.1/Documentation/arch/powerpc/
Dkvm-nested.rst12 hypervisor has implemented them. The terms L0, L1, and L2 are used to
16 and controlled by L0. L2 is a guest virtual machine that is initiated
39 call made by the L1 to tell the L0 to start an L2 vCPU with the given
40 state. The L0 then starts this L2 and runs until an L2 exit condition
41 is reached. Once the L2 exits, the state of the L2 is given back to
42 the L1 by the L0. The full L2 vCPU state is always transferred from
43 and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
44 vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
52 The L1 may run any L2 or vCPU without first informing the L0. It
61 The new PAPR API changes from the v1 API such that the creating L2 and
[all …]
/linux-6.12.1/arch/mips/cavium-octeon/
DKconfig31 bool "Lock often used kernel code in the L2"
34 Enable locking parts of the kernel into the L2 cache.
37 bool "Lock the TLB handler in L2"
41 Lock the low level TLB fast path into L2.
44 bool "Lock the exception handler in L2"
48 Lock the low level exception handler into L2.
51 bool "Lock the interrupt handler in L2"
55 Lock the low level interrupt handler into L2.
58 bool "Lock the 2nd level interrupt handler in L2"
62 Lock the 2nd level interrupt handler in L2.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/cache/
Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
/linux-6.12.1/arch/arc/kernel/
Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
209 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
335 ; However the context returning might not have taken L2 intr itself
[all …]
/linux-6.12.1/security/apparmor/include/
Dlabel.h163 #define next_comb(I, L1, L2) \ argument
166 if ((I).j >= (L2)->size) { \
174 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
253 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
[all …]
Dperms.h186 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
/linux-6.12.1/arch/arm/boot/dts/calxeda/
Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
/linux-6.12.1/Documentation/virt/kvm/x86/
Drunning-nested-guests.rst14 | L2 | | L2 |
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
139 .. note:: If you suspect your L2 (i.e. nested guest) is running slower,
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
193 "savevm"/"loadvm") until the L2 guest shuts down. Attempting to migrate
194 or save-and-load an L1 guest while an L2 guest is running will result in
199 actually running L2 guests, is expected to function normally even on AMD
202 Migrating an L2 guest is always expected to succeed, so all the following
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca9.dts44 next-level-cache = <&L2>;
51 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
166 L2: cache-controller@1e00a000 { label
227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
/linux-6.12.1/Documentation/locking/
Dlockdep-design.rst22 dependency can be understood as lock order, where L1 -> L2 suggests that
23 a task is attempting to acquire L2 while holding L1. From lockdep's
24 perspective, the two locks (L1 and L2) are not necessarily related; that
145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
523 , which means lockdep has seen L1 held before L2 held in the same context at runtime.
524 And in deadlock detection, we care whether we could get blocked on L2 with L1 held,
525 IOW, whether there is a locker L3 that L1 blocks L3 and L2 gets blocked by L3. So
526 we only care about 1) what L1 blocks and 2) what blocks L2. As a result, we can combine
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
/linux-6.12.1/Documentation/translations/it_IT/locking/
Dlockdep-design.rst21 possono essere interpretate come il loro ordine; per esempio L1 -> L2 suggerisce
22 che un processo cerca di acquisire L2 mentre già trattiene L1. Dal punto di
23 vista di lockdep, i due blocchi (L1 ed L2) non sono per forza correlati: quella
143 <L1> -> <L2>
144 <L2> -> <L1>
531 L1 -> L2
533 Questo significa che lockdep ha visto acquisire L1 prima di L2 nello stesso
535 interessa sapere se possiamo rimanere bloccati da L2 mentre L1 viene trattenuto.
537 da L1 e un L2 che viene bloccato da L3. Dunque, siamo interessati a (1) quello
538 che L1 blocca e (2) quello che blocca L2. Di conseguenza, possiamo combinare
[all …]
/linux-6.12.1/arch/powerpc/perf/
Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/linux-6.12.1/Documentation/networking/
Dipvlan.rst14 the master device share the L2 with its slave devices. I have developed this
45 (b) This command will create IPvlan link in L2 bridge mode::
49 (c) This command will create an IPvlan device in L2 private mode::
53 (d) This command will create an IPvlan device in L2 vepa mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
68 4.1 L2 mode:
81 master device for the L2 processing and routing from that instance will be
133 namespace where L2 on the slave could be changed / misused.
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
/linux-6.12.1/arch/alpha/kernel/
Dsetup.c1196 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1219 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1233 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1247 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1281 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1283 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1295 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1302 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1308 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1314 alpha_l2_cacheshape = L2; in determine_cpu_caches()
/linux-6.12.1/drivers/net/ethernet/intel/libie/
Drx.c36 LIBIE_RX_PT(L2, NOT_FRAG, NONE, NONE, NOT_FRAG, iprot, pl)
37 #define LIBIE_RX_PT_L2 __LIBIE_RX_PT_L2(NONE, L2)
38 #define LIBIE_RX_PT_TS __LIBIE_RX_PT_L2(TIMESYNC, L2)
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm4708.dtsi31 next-level-cache = <&L2>;
38 next-level-cache = <&L2>;
/linux-6.12.1/drivers/cache/
DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
/linux-6.12.1/Documentation/admin-guide/perf/
Dqcom_l2_pmu.rst5 This driver supports the L2 cache clusters found in Qualcomm Technologies
6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
9 There is one logical L2 PMU exposed, which aggregates the results from
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
/linux-6.12.1/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp30 next-level-cache = <&L2>;
39 next-level-cache = <&L2>;

12345678910>>...12