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Searched refs:HSYNC (Results 1 – 24 of 24) sorted by relevance

/linux-6.12.1/Documentation/admin-guide/media/
Dmgb4.rst108 The type of HSYNC pulses as detected by the video format detector.
119 HSYNC pulses, these must be generated internally in the FPGA to achieve
126 HSYNC pulses, these must be generated internally in the FPGA to achieve
129 internal HSYNC pulse. The value must be greater than 1 and smaller than
142 Width of the HSYNC signal in PCLK clock ticks.
154 Number of PCLK pulses between deassertion of the HSYNC signal and the first
162 line (marked by DE=1) and assertion of the HSYNC signal.
239 HSYNC signal polarity.
267 Width of the HSYNC signal in pixels. The default value is 40.
273 Number of PCLK pulses between deassertion of the HSYNC signal and the first
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/linux-6.12.1/drivers/gpu/drm/nouveau/dispnv50/
Ddac507d.c37 sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync); in dac507d_ctrl()
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a07g043u11-smarc-du-adv7513.dtso48 pinmux = <RZG2L_PORT_PINMUX(11, 0, 6)>, /* HSYNC */
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dtvp514x.txt17 - hsync-active: HSYNC Polarity configuration for endpoint.
Dtvp7002.txt10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
Dov7670.txt13 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
Dtvp5150.txt44 - hsync-active: Active state of the HSYNC signal. Must be <1> (HIGH).
/linux-6.12.1/Documentation/fb/
Dpxafb.rst39 hsynclen:HSYNC == LCCR1_HSW + 1
65 hsync:HSYNC, vsync:VSYNC
Dmatroxfb.rst271 left:X left boundary: pixels between end of HSYNC pulse and first pixel.
273 right:X right boundary: pixels between end of picture and start of HSYNC
275 hslen:X length of HSYNC pulse, in pixels. Default is derived from `vesa`
279 sync:X sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
280 If bit 3 (value 0x08) is set, composite sync instead of HSYNC is
/linux-6.12.1/drivers/video/fbdev/i810/
Di810_regs.h150 #define HSYNC 0x60008 macro
/linux-6.12.1/include/video/
Dsstfb.h161 #define HSYNC 0x0220 macro
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx53-mba53.dts138 /* VGA_VSYNC, HSYNC with max drive strength */
Dimx6ul-tx6ul-mainboard.dts205 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
Dimx6ul-tx6ul.dtsi591 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
624 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
Dimx6qdl-kontron-samx6i.dtsi604 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dam437x-sbc-t43.dts60 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
Dam437x-sk-evm.dts372 AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
Dam43x-epos-evm.dts433 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
Dam437x-gp-evm.dts293 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
/linux-6.12.1/drivers/gpu/drm/i2c/
Dch7006_mode.c122 .flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
/linux-6.12.1/drivers/pinctrl/renesas/
Dpfc-sh7786.c524 GPIO_FN(HSYNC),
/linux-6.12.1/drivers/video/fbdev/
Dsstfb.c535 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); in sstfb_set_par()
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91sam9g45.dtsi283 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
/linux-6.12.1/drivers/gpu/drm/
Ddrm_modes.c1740 MODE_STATUS(HSYNC),