Lines Matching refs:HSYNC

108     The type of HSYNC pulses as detected by the video format detector.
119     HSYNC pulses, these must be generated internally in the FPGA to achieve
126     HSYNC pulses, these must be generated internally in the FPGA to achieve
129     internal HSYNC pulse. The value must be greater than 1 and smaller than
142     Width of the HSYNC signal in PCLK clock ticks.
154     Number of PCLK pulses between deassertion of the HSYNC signal and the first
162     line (marked by DE=1) and assertion of the HSYNC signal.
239     HSYNC signal polarity.
267     Width of the HSYNC signal in pixels. The default value is 40.
273     Number of PCLK pulses between deassertion of the HSYNC signal and the first
278     line (marked by DE=1) and assertion of the HSYNC signal. The default value