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Searched refs:DISP_CC_MDSS_BYTE1_CLK (Results 1 – 24 of 24) sorted by relevance

/linux-6.12.1/include/dt-bindings/clock/
Dqcom,dispcc-sdm845.h15 #define DISP_CC_MDSS_BYTE1_CLK 5 macro
Dqcom,dispcc-sm8150.h16 #define DISP_CC_MDSS_BYTE1_CLK 6 macro
Dqcom,dispcc-sm8350.h16 #define DISP_CC_MDSS_BYTE1_CLK 6 macro
Dqcom,dispcc-sm8250.h16 #define DISP_CC_MDSS_BYTE1_CLK 6 macro
Dqcom,dispcc-sc8280xp.h21 #define DISP_CC_MDSS_BYTE1_CLK 11 macro
Dqcom,x1e80100-dispcc.h18 #define DISP_CC_MDSS_BYTE1_CLK 8 macro
Dqcom,sm8550-dispcc.h18 #define DISP_CC_MDSS_BYTE1_CLK 8 macro
Dqcom,sm8650-dispcc.h18 #define DISP_CC_MDSS_BYTE1_CLK 8 macro
Dqcom,sm8450-dispcc.h17 #define DISP_CC_MDSS_BYTE1_CLK 7 macro
/linux-6.12.1/drivers/clk/qcom/
Ddispcc-sdm845.c779 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
Ddispcc-sm8250.c1165 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
Ddispcc-sc8280xp.c2890 [DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr,
2972 [DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr,
Ddispcc-x1e80100.c1546 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
Ddispcc-sm8450.c1639 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
Ddispcc-sm8550.c1647 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsdm670.dtsi1579 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsc8180x.dtsi3157 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8350.dtsi2798 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8150.dtsi4058 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8450.dtsi3348 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsdm845.dtsi4767 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8550.dtsi3148 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8650.dtsi3662 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
Dsm8250.dtsi4939 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,