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Searched refs:BIT_ULL (Results 1 – 25 of 573) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/panfrost/
Dpanfrost_issues.h142 BIT_ULL(HW_ISSUE_9435))
145 BIT_ULL(HW_ISSUE_6367) | \
146 BIT_ULL(HW_ISSUE_6787) | \
147 BIT_ULL(HW_ISSUE_8408) | \
148 BIT_ULL(HW_ISSUE_9510) | \
149 BIT_ULL(HW_ISSUE_10649) | \
150 BIT_ULL(HW_ISSUE_10676) | \
151 BIT_ULL(HW_ISSUE_10883) | \
152 BIT_ULL(HW_ISSUE_11020) | \
153 BIT_ULL(HW_ISSUE_11035) | \
[all …]
Dpanfrost_features.h29 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
30 BIT_ULL(HW_FEATURE_V4))
37 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
38 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
39 BIT_ULL(HW_FEATURE_XAFFINITY) | \
40 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT))
51 BIT_ULL(HW_FEATURE_JOBCHAIN_DISAMBIGUATION) | \
52 BIT_ULL(HW_FEATURE_PWRON_DURING_PWROFF_TRANS) | \
53 BIT_ULL(HW_FEATURE_XAFFINITY) | \
54 BIT_ULL(HW_FEATURE_THREAD_GROUP_SPLIT) | \
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dcpu.h360 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
361 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
362 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
363 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
364 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
365 #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
366 #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
367 #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
368 #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
369 #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
[all …]
/linux-6.12.1/drivers/mmc/host/
Dcavium.h120 #define MIO_EMM_DMA_FIFO_CFG_CLR BIT_ULL(16)
124 #define MIO_EMM_DMA_FIFO_CMD_RW BIT_ULL(62)
125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8 BIT_ULL(57)
129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
132 #define MIO_EMM_CMD_SKIP_BUSY BIT_ULL(62)
134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/thunder/
Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
40 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
87 #define SPU_CTL_LOW_POWER BIT_ULL(11)
88 #define SPU_CTL_LOOPBACK BIT_ULL(14)
89 #define SPU_CTL_RESET BIT_ULL(15)
91 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
93 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
[all …]
/linux-6.12.1/drivers/ras/amd/atl/
Ddehash.c20 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df2_dehash_addr()
23 hashed_bit ^= FIELD_GET(BIT_ULL(12), ctx->ret_addr); in df2_dehash_addr()
24 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr); in df2_dehash_addr()
25 hashed_bit ^= FIELD_GET(BIT_ULL(21), ctx->ret_addr); in df2_dehash_addr()
26 hashed_bit ^= FIELD_GET(BIT_ULL(30), ctx->ret_addr); in df2_dehash_addr()
29 ctx->ret_addr ^= BIT_ULL(intlv_bit_pos); in df2_dehash_addr()
44 intlv_bit = !!(BIT_ULL(intlv_bit_pos) & ctx->ret_addr); in df3_dehash_addr()
47 hashed_bit ^= FIELD_GET(BIT_ULL(14), ctx->ret_addr); in df3_dehash_addr()
48 hashed_bit ^= FIELD_GET(BIT_ULL(18), ctx->ret_addr) & hash_ctl_64k; in df3_dehash_addr()
49 hashed_bit ^= FIELD_GET(BIT_ULL(23), ctx->ret_addr) & hash_ctl_2M; in df3_dehash_addr()
[all …]
/linux-6.12.1/arch/loongarch/include/asm/
Dcpu.h106 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
107 #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
108 #define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
109 #define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
110 #define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
111 #define LOONGARCH_CPU_LASX BIT_ULL(CPU_FEATURE_LASX)
112 #define LOONGARCH_CPU_CRC32 BIT_ULL(CPU_FEATURE_CRC32)
113 #define LOONGARCH_CPU_COMPLEX BIT_ULL(CPU_FEATURE_COMPLEX)
114 #define LOONGARCH_CPU_CRYPTO BIT_ULL(CPU_FEATURE_CRYPTO)
115 #define LOONGARCH_CPU_LVZ BIT_ULL(CPU_FEATURE_LVZ)
[all …]
/linux-6.12.1/drivers/iommu/intel/
Dcap_audit.h13 #define CAP_FL5LP_MASK BIT_ULL(60)
14 #define CAP_PI_MASK BIT_ULL(59)
15 #define CAP_FL1GP_MASK BIT_ULL(56)
16 #define CAP_RD_MASK BIT_ULL(55)
17 #define CAP_WD_MASK BIT_ULL(54)
20 #define CAP_PSI_MASK BIT_ULL(39)
23 #define CAP_ZLR_MASK BIT_ULL(22)
26 #define CAP_CM_MASK BIT_ULL(7)
27 #define CAP_PHMR_MASK BIT_ULL(6)
28 #define CAP_PLMR_MASK BIT_ULL(5)
[all …]
/linux-6.12.1/drivers/infiniband/hw/irdma/
Ddefs.h384 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
387 #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
388 #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
390 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
391 #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
392 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
393 #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
397 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
400 #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
401 #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
[all …]
Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
18 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
39 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
45 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_gtt_defs.h9 #define XELPG_GGTT_PTE_PAT0 BIT_ULL(52)
10 #define XELPG_GGTT_PTE_PAT1 BIT_ULL(53)
16 #define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62)
17 #define XE2_PPGTT_PTE_PAT4 BIT_ULL(61)
18 #define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12)
19 #define XE_PPGTT_PTE_PAT2 BIT_ULL(7)
20 #define XE_PPGTT_PTE_PAT1 BIT_ULL(4)
21 #define XE_PPGTT_PTE_PAT0 BIT_ULL(3)
23 #define XE_PDE_PS_2M BIT_ULL(7)
24 #define XE_PDPE_PS_1G BIT_ULL(7)
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_flow.h15 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
16 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
18 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
19 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
21 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
22 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
24 (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
25 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
27 (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
28 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
[all …]
/linux-6.12.1/arch/x86/include/asm/
Dmce.h13 #define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
14 #define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
16 #define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */
20 #define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
21 #define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
22 #define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
25 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
26 #define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
27 #define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
[all …]
Dmsr-index.h98 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
274 #define LBR_INFO_MISPRED BIT_ULL(63)
275 #define LBR_INFO_IN_TX BIT_ULL(62)
276 #define LBR_INFO_ABORT BIT_ULL(61)
277 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
308 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
309 #define PERF_CAP_ARCH_REG BIT_ULL(7)
311 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
331 #define RTIT_CTL_NOTNT BIT_ULL(55)
395 #define MSR_IA32_PASID_VALID BIT_ULL(31)
[all …]
/linux-6.12.1/drivers/gpu/drm/arm/display/komeda/
Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
24 #define KOMEDA_EVENT_EMPTY BIT_ULL(8)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
[all …]
/linux-6.12.1/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.h744 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
745 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
746 BIT_ULL(MTK_CLK_TRGPLL))
747 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
748 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
749 BIT_ULL(MTK_CLK_GP2) | \
750 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
751 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
752 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
753 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep_vf/
Doctep_vf_regs_cn9k.h20 #define CN93_VF_RING_OFFSET BIT_ULL(17)
69 #define CN93_VF_R_IN_CTL_IDLE BIT_ULL(28)
71 #define CN93_VF_R_IN_CTL_IS_64B BIT_ULL(24)
72 #define CN93_VF_R_IN_CTL_D_NSR BIT_ULL(8)
73 #define CN93_VF_R_IN_CTL_D_ESR BIT_ULL(6)
74 #define CN93_VF_R_IN_CTL_D_ROR BIT_ULL(5)
75 #define CN93_VF_R_IN_CTL_NSR BIT_ULL(3)
76 #define CN93_VF_R_IN_CTL_ESR BIT_ULL(1)
77 #define CN93_VF_R_IN_CTL_ROR BIT_ULL(0)
120 #define CN93_VF_R_OUT_INT_LEVELS_BMODE BIT_ULL(63)
[all …]
/linux-6.12.1/drivers/vdpa/pds/
Ddebugfs.c54 u64 mask = BIT_ULL(i); in print_feature_bits_all()
57 case BIT_ULL(VIRTIO_NET_F_CSUM): in print_feature_bits_all()
60 case BIT_ULL(VIRTIO_NET_F_GUEST_CSUM): in print_feature_bits_all()
63 case BIT_ULL(VIRTIO_NET_F_CTRL_GUEST_OFFLOADS): in print_feature_bits_all()
66 case BIT_ULL(VIRTIO_NET_F_MTU): in print_feature_bits_all()
69 case BIT_ULL(VIRTIO_NET_F_MAC): in print_feature_bits_all()
72 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO4): in print_feature_bits_all()
75 case BIT_ULL(VIRTIO_NET_F_GUEST_TSO6): in print_feature_bits_all()
78 case BIT_ULL(VIRTIO_NET_F_GUEST_ECN): in print_feature_bits_all()
81 case BIT_ULL(VIRTIO_NET_F_GUEST_UFO): in print_feature_bits_all()
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/include/x86_64/
Dpmu.h28 #define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16)
29 #define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17)
30 #define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18)
31 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19)
32 #define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20)
33 #define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21)
34 #define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22)
35 #define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23)
39 #define INTEL_RDPMC_METRICS BIT_ULL(29)
40 #define INTEL_RDPMC_FIXED BIT_ULL(30)
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Drpm.h20 #define RPMX_RX_TS_PREPEND BIT_ULL(22)
21 #define RPMX_TX_PTP_1S_SUPPORT BIT_ULL(17)
28 #define RPMX_MTI_PCS_LBK BIT_ULL(14)
34 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE BIT_ULL(29)
35 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE BIT_ULL(28)
36 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE BIT_ULL(8)
37 #define RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE BIT_ULL(19)
55 #define RPMX_CMR_RX_OVR_BP_EN(x) BIT_ULL((x) + 8)
56 #define RPMX_CMR_RX_OVR_BP_BP(x) BIT_ULL((x) + 4)
63 #define RPM_TX_EN BIT_ULL(0)
[all …]
/linux-6.12.1/drivers/firmware/efi/
Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
29 #define INFO_VALID_CHECK_INFO BIT_ULL(0)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
31 #define INFO_VALID_REQUESTOR_ID BIT_ULL(2)
32 #define INFO_VALID_RESPONDER_ID BIT_ULL(3)
33 #define INFO_VALID_IP BIT_ULL(4)
35 #define CHECK_VALID_TRANS_TYPE BIT_ULL(0)
36 #define CHECK_VALID_OPERATION BIT_ULL(1)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
[all …]
/linux-6.12.1/include/media/
Drc-map.h15 #define RC_PROTO_BIT_UNKNOWN BIT_ULL(RC_PROTO_UNKNOWN)
16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
18 #define RC_PROTO_BIT_RC5X_20 BIT_ULL(RC_PROTO_RC5X_20)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
21 #define RC_PROTO_BIT_SONY12 BIT_ULL(RC_PROTO_SONY12)
22 #define RC_PROTO_BIT_SONY15 BIT_ULL(RC_PROTO_SONY15)
23 #define RC_PROTO_BIT_SONY20 BIT_ULL(RC_PROTO_SONY20)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/idpf/
Didpf_lan_txrx.h41 (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
42 BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
43 BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
44 BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
45 BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
46 BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
47 BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
48 BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
49 BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
50 BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/
Di915_gem_gtt.h41 #define PIN_NOEVICT BIT_ULL(0)
42 #define PIN_NOSEARCH BIT_ULL(1)
43 #define PIN_NONBLOCK BIT_ULL(2)
44 #define PIN_MAPPABLE BIT_ULL(3)
45 #define PIN_ZONE_4G BIT_ULL(4)
46 #define PIN_HIGH BIT_ULL(5)
47 #define PIN_OFFSET_BIAS BIT_ULL(6)
48 #define PIN_OFFSET_FIXED BIT_ULL(7)
49 #define PIN_OFFSET_GUARD BIT_ULL(8)
50 #define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */
[all …]
/linux-6.12.1/tools/arch/x86/include/asm/
Dmsr-index.h98 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
274 #define LBR_INFO_MISPRED BIT_ULL(63)
275 #define LBR_INFO_IN_TX BIT_ULL(62)
276 #define LBR_INFO_ABORT BIT_ULL(61)
277 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
308 #define PERF_CAP_PEBS_TRAP BIT_ULL(6)
309 #define PERF_CAP_ARCH_REG BIT_ULL(7)
311 #define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
331 #define RTIT_CTL_NOTNT BIT_ULL(55)
395 #define MSR_IA32_PASID_VALID BIT_ULL(31)
[all …]

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