| /linux-6.12.1/drivers/scsi/ |
| D | dc395x.h | 71 #define BIT5 0x00000020 macro
134 #define SRB_ERROR BIT5
139 #define RESIDUAL_VALID BIT5
170 #define EN_TAG_QUEUEING BIT5
597 #define LUN_CHECK BIT5
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| /linux-6.12.1/drivers/staging/rtl8723bs/include/ |
| D | hal_pwr_seq.h | 45 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b…
74 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b…
144 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK …
175 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TS…
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| D | rtl8723b_spec.h | 170 #define BIT_BCN_PORT_SEL BIT5
209 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
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| D | hal_com_reg.h | 212 #define HSISR_SPS_OCP_INT BIT5
556 #define SDIO_HISR_RXFOVW BIT5
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| D | osdep_service.h | 22 #define BIT5 0x00000020 macro
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| /linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| D | pwrseq.h | 262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
383 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
619 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
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| /linux-6.12.1/drivers/video/fbdev/via/ |
| D | dvi.c | 62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
408 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
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| D | hw.c | 1696 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1702 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2065 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
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| D | share.h | 19 #define BIT5 0x20 macro
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| /linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 36 #define BIT5 0x00000020 macro
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| D | halbtc8821a1ant.h | 10 #define BT_INFO_8821A_1ANT_B_HID BIT5
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| D | halbtc8821a2ant.h | 10 #define BT_INFO_8821A_2ANT_B_HID BIT5
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| D | halbtc8192e2ant.h | 9 #define BT_INFO_8192E_2ANT_B_HID BIT5
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| D | halbtc8723b2ant.h | 12 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| D | halbtc8723b1ant.h | 9 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| D | halbtcoutsrc.h | 97 #define ALGO_TRACE_FW_DETAIL BIT5
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| D | halbtc8821a1ant.c | 833 if (byte1 & BIT4 && !(byte1 & BIT5)) { in btc8821a1ant_set_fw_ps_tdma()
837 real_byte1 |= BIT5; in btc8821a1ant_set_fw_ps_tdma()
839 real_byte5 |= BIT5; in btc8821a1ant_set_fw_ps_tdma()
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| /linux-6.12.1/drivers/staging/rtl8723bs/hal/ |
| D | HalBtc8723b2Ant.h | 10 #define BT_INFO_8723B_2ANT_B_HID BIT5
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| D | HalBtc8723b1Ant.h | 10 #define BT_INFO_8723B_1ANT_B_HID BIT5
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| D | odm.h | 370 ODM_BB_CCK_PD = BIT5,
447 ODM_WM_AUTO = BIT5,
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| D | HalBtc8723b1Ant.c | 998 if (byte1 & BIT4 && !(byte1 & BIT5)) { in halbtc8723b1ant_SetFwPstdma()
1000 realByte1 |= BIT5; in halbtc8723b1ant_SetFwPstdma()
1002 realByte5 |= BIT5; in halbtc8723b1ant_SetFwPstdma()
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| /linux-6.12.1/drivers/tty/ |
| D | synclink_gt.c | 391 #define IRQ_DCD BIT5
2134 if (status & (BIT5 + BIT4)) { in isr_rdma()
2159 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4040 case 7: val |= BIT5; break; in async_mode()
4041 case 8: val |= BIT5 + BIT4; break; in async_mode()
4080 case 7: val |= BIT5; break; in async_mode()
4081 case 8: val |= BIT5 + BIT4; break; in async_mode()
4204 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4206 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4292 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
[all …]
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| /linux-6.12.1/include/uapi/linux/ |
| D | synclink.h | 24 #define BIT5 0x0020 macro
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| /linux-6.12.1/lib/zstd/common/ |
| D | zstd_internal.h | 68 #define BIT5 32 macro
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| /linux-6.12.1/drivers/staging/rtl8723bs/core/ |
| D | rtw_mlme.c | 2159 if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5)) in rtw_ht_use_default_setting()
2167 if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5)) in rtw_ht_use_default_setting()
2183 if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) in rtw_ht_use_default_setting()
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