391 #define IRQ_DCD     BIT5
2134 	if (status & (BIT5 + BIT4)) {  in isr_rdma()
2159 	if (status & (BIT5 + BIT4 + BIT3)) {  in isr_tdma()
4040 	case 7: val |= BIT5; break;  in async_mode()
4041 	case 8: val |= BIT5 + BIT4; break;  in async_mode()
4080 	case 7: val |= BIT5; break;  in async_mode()
4081 	case 8: val |= BIT5 + BIT4; break;  in async_mode()
4204 	case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;  in sync_mode()
4206 	case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;  in sync_mode()
4292 			val |= BIT6 + BIT5;	/* 011, txclk = BRG/16 */  in sync_mode()
4299 		val |= BIT5;	/* 001, txclk = RXC Input */  in sync_mode()
4377 		tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;  in tx_set_idle()
4382 		tcr &= ~(BIT5 + BIT4);  in tx_set_idle()
4444 		val |= BIT5; /* 0010 */  in msc_set_vcr()
4447 		val |= BIT7 + BIT6 + BIT5; /* 1110 */  in msc_set_vcr()
4854 	info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;  in register_test()