| /linux-6.12.1/drivers/scsi/ |
| D | dc395x.h | 74 #define BIT2 0x00000004 macro
81 #define FORMATING_MEDIA BIT2
87 #define ASPI_SUPPORT BIT2
123 #define RESET_DONE BIT2
131 #define OVER_RUN BIT2
141 #define RESET_DEV0 BIT2
167 #define WIDE_NEGO_ENABLE BIT2
594 #define RST_SCSI_BUS BIT2
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| /linux-6.12.1/drivers/staging/rtl8723bs/include/ |
| D | hal_com_reg.h | 222 #define RRSR_5_5M BIT2
257 #define BW_OPMODE_20MHZ BIT2
292 #define RCR_AM BIT2 /* Accept multicast packet */
553 #define SDIO_HISR_TXERR BIT2
598 #define WL_FUNC_EN BIT2 /* WiFi function enable */
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| D | hal_pwr_seq.h | 46 …AB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW …
103 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1…
176 …_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
201 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/…
203 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/…
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| D | rtl8723b_spec.h | 212 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
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| D | osdep_service.h | 19 #define BIT2 0x00000004 macro
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| D | rtw_mlme.h | 118 RTW_ROAM_ACTIVE = BIT2,
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| /linux-6.12.1/drivers/video/fbdev/via/ |
| D | dvi.c | 335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
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| D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
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| D | share.h | 16 #define BIT2 0x04 macro
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| /linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| D | pwrseq.h | 26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
523 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
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| /linux-6.12.1/drivers/staging/rtl8723bs/hal/ |
| D | HalHWImg8723B_MAC.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
60 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| D | HalHWImg8723B_RF.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
66 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| D | HalHWImg8723B_BB.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
61 if ((cond1 & BIT2) != 0) /* ALNA */ in CheckPositive()
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| D | HalBtc8723b2Ant.h | 13 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
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| D | HalBtc8723b1Ant.h | 13 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
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| D | HalBtcOutSrc.h | 74 #define WIFI_HS_CONNECTED BIT2
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| /linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 33 #define BIT2 0x00000004 macro
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| D | halbtcoutsrc.h | 89 #define INTF_NOTIFY BIT2
94 #define ALGO_BT_MONITOR BIT2
106 #define WIFI_HS_CONNECTED BIT2
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| D | halbtc8821a1ant.h | 13 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
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| D | halbtc8821a2ant.h | 13 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
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| D | halbtc8192e2ant.h | 12 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
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| D | halbtc8723b2ant.h | 15 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
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| D | halbtc8723b1ant.h | 12 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
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| /linux-6.12.1/drivers/tty/ |
| D | synclink_gt.c | 192 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
1934 if (status & BIT2) { in cts_change()
2204 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
3804 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3853 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
3878 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
3900 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3903 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
3920 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3949 wr_reg32(info, TDCSR, BIT2 + BIT0); in tx_start()
[all …]
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| /linux-6.12.1/include/uapi/linux/ |
| D | synclink.h | 21 #define BIT2 0x0004 macro
|