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Searched refs:BIT1 (Results 1 – 25 of 50) sorted by relevance

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/linux-6.12.1/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h48 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x…
56 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin…
57 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 …
58 …{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
60 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR …
69 …{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
71 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 …
72 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x…
87 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power s…
94 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
[all …]
Drtw_ht.h65 #define LDPC_HT_ENABLE_TX BIT1
69 #define STBC_HT_ENABLE_TX BIT1
73 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
Dhal_com_reg.h221 #define RRSR_2M BIT1
293 #define RCR_APM BIT1 /* Accept physical match packet */
548 #define SDIO_HIMR_AVAL_MSK BIT1
552 #define SDIO_HISR_AVAL BIT1
597 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */
Dhal_phy.h14 #define ANT_DETECT_BY_RSSI BIT1
Drtl8723b_spec.h213 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
Dosdep_service.h18 #define BIT1 0x00000002 macro
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
[all …]
/linux-6.12.1/drivers/scsi/
Ddc395x.h75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
593 #define GREATER_1G BIT1
/linux-6.12.1/drivers/video/fbdev/via/
Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
Dvia_utility.c170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
Dshare.h15 #define BIT1 0x02 macro
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h32 #define BIT1 0x00000002 macro
Dhalbtc8821a1ant.h14 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
Dhalbtc8821a2ant.h14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
Dhalbtc8192e2ant.h13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
Dhalbtc8723b2ant.h16 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
Dhalbtc8723b1ant.h13 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
/linux-6.12.1/drivers/tty/
Dsynclink_gt.c193 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
351 #define MASK_PARITY BIT1
1782 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1784 if (status & BIT1) in rx_async()
1791 if (status & BIT1) in rx_async()
1969 if (status & BIT1) { in dcd_change()
3775 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3788 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3852 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
3877 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
[all …]
/linux-6.12.1/drivers/staging/rtl8723bs/hal/
Dodm_DIG.h82 ODM_RESUME_DIG = BIT1
DHalHWImg8723B_MAC.c58 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
DHalBtc8723b2Ant.h14 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
DHalBtc8723b1Ant.h14 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
DHalHWImg8723B_RF.c64 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
/linux-6.12.1/include/uapi/linux/
Dsynclink.h20 #define BIT1 0x0002 macro

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