193 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
351 #define MASK_PARITY  BIT1
1782 			status = *(p + 1) & (BIT1 + BIT0);  in rx_async()
1784 				if (status & BIT1)  in rx_async()
1791 				if (status & BIT1)  in rx_async()
1969 	if (status & BIT1) {  in dcd_change()
3775 	wr_reg32(info, RDCSR, BIT1);  in rdma_reset()
3788 	wr_reg32(info, TDCSR, BIT1);  in tdma_reset()
3852 	val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */  in rx_stop()
3877 	val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */  in rx_start()
3910 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
3920 			 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));  in tx_start()
3963 	val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */  in tx_stop()
4309 		val |= BIT1 + BIT0;  in sync_mode()
4419 	if (status & BIT1)  in get_gtsignals()
4461 		val |= BIT1;  in msc_set_vcr()
4577 		status &= ~BIT1;  in rx_get_frame()
4588 	} else if (status & BIT1) {  in rx_get_frame()
4632 				*p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;  in rx_get_frame()
4875 		(unsigned short)(rd_reg16(info, TCR) | BIT1));  in irq_test()