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Searched refs:BIT0 (Results 1 – 25 of 51) sorted by relevance

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/linux-6.12.1/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h42 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b…
47 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB …
49 …{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0…
50 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
53 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling unti…
54 …_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
59 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR …
70 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
75 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b…
86 … PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO sus…
[all …]
Drtw_ht.h64 #define LDPC_HT_ENABLE_RX BIT0
68 #define STBC_HT_ENABLE_RX BIT0
72 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
Dhal_com_reg.h211 #define HSISR_GPIO12_0_INT BIT0
220 #define RRSR_1M BIT0
547 #define SDIO_HIMR_RX_REQUEST_MSK BIT0
551 #define SDIO_HISR_RX_REQUEST BIT0
Dhal_phy.h13 #define ANT_DETECT_BY_SINGLE_TONE BIT0
Drtl8723b_spec.h214 #define IMR_ROK_8723B BIT0 /* Receive DMA OK */
Dosdep_service.h17 #define BIT0 0x00000001 macro
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
371 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
389 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/linux-6.12.1/drivers/video/fbdev/via/
Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
583 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
659 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
844 bdithering = BIT0; in fill_lcd_format()
[all …]
Dvia_utility.c152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dhw.c472 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
949 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
986 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
987 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
1667 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1681 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1688 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
/linux-6.12.1/drivers/scsi/
Ddc395x.h76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
165 #define SYNC_NEGO_ENABLE BIT0
592 #define MORE2_DRV BIT0
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8821a1ant.h15 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtc8723b1ant.h14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
17 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbt_precomp.h31 #define BIT0 0x00000001 macro
Dhalbtcoutsrc.h88 #define INTF_INIT BIT0
92 #define ALGO_BT_RSSI_STATE BIT0
104 #define WIFI_STA_CONNECTED BIT0
Dhalbtc8821a2ant.h15 #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
Dhalbtc8192e2ant.h14 #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
/linux-6.12.1/drivers/staging/rtl8723bs/hal/
DHalBtc8723b1Ant.h15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_ & BIT0)) ? true : false)
Dodm_reg.h89 #define BIT_FA_RESET BIT0
Dodm_HWConfig.c338 pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; in odm_Process_RSSIForDM()
372 OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0; in odm_Process_RSSIForDM()
Dodm_DIG.h81 ODM_PAUSE_DIG = BIT0,
DHalHWImg8723B_MAC.c56 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
DHalBtc8723b2Ant.h15 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
/linux-6.12.1/drivers/tty/
Dsynclink_gt.c187 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
194 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
352 #define MASK_FRAMING BIT0
394 #define IRQ_MASTER BIT0
1782 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1786 else if (status & BIT0) in rx_async()
1793 else if (status & BIT0) in rx_async()
2006 if (status & BIT0) { in ri_change()
3779 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3792 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
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