Lines Matching refs:BIT0
45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
408 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
421 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
462 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); in viafb_dvi_enable()