Searched refs:BANK_HEIGHT (Results 1 – 15 of 15) sorted by relevance
85 #define BANK_HEIGHT(x) ((x) << 16) macro409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()425 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()460 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v6_0_tiling_mode_table_init()480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v6_0_tiling_mode_table_init()[all …]
74 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) macro2192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()2208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v8_0_tiling_mode_table_init()2212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()2220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v8_0_tiling_mode_table_init()2224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v8_0_tiling_mode_table_init()[all …]
1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1124 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in gfx_v7_0_tiling_mode_table_init()1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1132 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | in gfx_v7_0_tiling_mode_table_init()1152 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()1156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in gfx_v7_0_tiling_mode_table_init()[all …]
195 # define BANK_HEIGHT(x) ((x) << 2) macro
1208 # define BANK_HEIGHT(x) ((x) << 16) macro
1960 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1929 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1990 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
2040 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2547 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()2565 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in si_tiling_mode_table_init()2574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()2583 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in si_tiling_mode_table_init()[all …]
2437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2449 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()2465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | in cik_tiling_mode_table_init()2469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | in cik_tiling_mode_table_init()2473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()[all …]
1211 # define BANK_HEIGHT(x) ((x) << 16) macro
1265 # define BANK_HEIGHT(x) ((x) << 2) macro
187 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
1755 typedef enum BANK_HEIGHT { enum1760 } BANK_HEIGHT; typedef