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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dcdns,xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Cadence XSPI Controller
11 - Parshuram Thombare <pthombar@cadence.com>
14 The XSPI controller allows SPI protocol communication in
16 read/write access to slaves such as SPI-NOR flash.
21 - cdns,xspi-nor
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/linux-6.12.1/drivers/mtd/spi-nor/
Dspansion.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mtd/spi-nor.h>
48 /* Cypress SPI NOR flash operations. */
68 * struct spansion_nor_params - Spansion private parameters.
77 * spansion_nor_clear_sr() - Clear the Status Register.
78 * @nor: pointer to 'struct spi_nor'.
80 static void spansion_nor_clear_sr(struct spi_nor *nor) in spansion_nor_clear_sr() argument
82 const struct spansion_nor_params *priv_params = nor->params->priv; in spansion_nor_clear_sr()
85 if (nor->spimem) { in spansion_nor_clear_sr()
86 struct spi_mem_op op = SPANSION_OP(priv_params->clsr); in spansion_nor_clear_sr()
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Dsfdp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mtd/spi-nor.h>
14 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
16 (((p)->parameter_table_pointer[2] << 16) | \
17 ((p)->parameter_table_pointer[1] << 8) | \
18 ((p)->parameter_table_pointer[0] << 0))
19 #define SFDP_PARAM_HEADER_PARAM_LEN(p) ((p)->length * 4)
23 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
24 #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 table. */
31 * Register Map Offsets for Multi-Chip
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Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
49 * @nor: pointer to a 'struct spi_nor'
57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, in spi_nor_get_cmd_ext() argument
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
65 return op->cmd.opcode; in spi_nor_get_cmd_ext()
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/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
128 to SPI NOR chips, and support for the SPI flash memory
130 only supports SPI NOR.
155 supports spi-mem interface.
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Dspi-cadence-xspi.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Cadence XSPI flash controller driver
3 // Copyright (C) 2020-21 Cadence
19 #include <linux/spi/spi-mem.h>
27 #define CDNS_XSPI_NAME "cadence-xspi"
31 * configure XSPI controller pin-strap settings
157 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
160 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
161 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \
162 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
18 obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
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