| /linux-6.12.1/Documentation/driver-api/md/ |
| D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported
8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since
9 3.4) has a new option '--write-journal' to create array with cache. Please
11 in write-through mode. A user can switch it to write-back mode by::
13 echo "write-back" > /sys/block/md0/md/journal_mode
15 And switch it back to write-through mode by::
17 echo "write-through" > /sys/block/md0/md/journal_mode
22 write-through mode
25 This mode mainly fixes the 'write hole' issue. For RAID 4/5/6 array, an unclean
27 and parity don't match. The reason is that a stripe write involves several RAID
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-class-bdi | 14 non-block filesystems which provide their own BDI, such as NFS
17 MAJOR:MINOR-fuseblk
23 The default backing dev, used for non-block device backed
30 Size of the read-ahead window in kilobytes
32 (read-write)
38 total write-back cache that relates to its current average
42 percentage of the write-back cache to a particular device.
45 (read-write)
52 total write-back cache that relates to its current average
56 of the write-back cache to a particular device. The value is
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| D | debugfs-scmi-raw | 5 Description: SCMI Raw synchronous message injection/snooping facility; write
7 in little-endian binary format to have it sent to the configured
11 Each write to the entry causes one command request to be built
12 and sent while the replies are read back one message at time
20 Description: SCMI Raw asynchronous message injection/snooping facility; write
22 in little-endian binary format to have it sent to the configured
29 Each write to the entry causes one command request to be built
30 and sent while the replies are read back one message at time
38 Description: SCMI Raw message errors facility; any kind of timed-out or
41 Each read gives back one message at time (receiving an EOF at
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/ |
| D | recommended.json | 9 "PublicDescription": "Attributable Level 1 data cache access, write",
12 "BriefDescription": "L1D cache access, write"
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
24 "BriefDescription": "L1D cache refill, write"
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
63 "PublicDescription": "Attributable Level 1 data TLB refill, write",
66 "BriefDescription": "L1D tlb refill, write"
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| /linux-6.12.1/include/linux/ |
| D | counter.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
40 * struct counter_comp - Counter component node
42 * @name: device-specific component name
43 * @priv: component-relevant data
45 * respective Synapse action mode should be passed back via
48 * respective Device u8 component should be passed back via
51 * respective Count u8 component should be passed back via
54 * respective Signal u8 component should be passed back via
58 * back via the val parameter.
60 * respective Count u32 component should be passed back via
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| D | pstore_zone.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct pstore_zone_info - pstore/zone back-end driver structure
14 * @owner: Module which is responsible for this back-end driver.
15 * @name: Name of the back-end driver.
28 * @write: The same as @read, but the following error number:
29 * -EBUSY means try to write again later.
30 * -ENOMSG means to try next zone.
35 * @panic_write:The write operation only used for panic case. It's optional
39 * excluding -ENOMSG mean error. -ENOMSG means to try next zone.
52 pstore_zone_write_op write; member
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| /linux-6.12.1/Documentation/scsi/ |
| D | sd-parameters.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ---------------
9 Enable/disable drive write & read cache.
12 cache_type string WCE RCD Write cache Read cache
14 write through 0 0 off on
16 write back 1 0 on on
17 write back, no read (daft) 1 1 on off
20 To set cache type to "write back" and save this setting to the drive::
22 # echo "write back" > cache_type
27 # echo "temporary write back" > cache_type
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| /linux-6.12.1/arch/m68k/include/asm/ |
| D | traps.h | 122 #define MMU_WP (0x0800) /* write-protected */
142 /* bits for 68040 write back status word */
173 #define MMU060_RW (0x01800000) /* read/write */
174 # define MMU060_RW_W (0x00800000) /* write */
176 # define MMU060_RW_RMW (0x01800000) /* read/modify/write */
177 # define MMU060_W (0x00800000) /* general write, includes rmw */
189 #define MMU060_WP (0x00000080) /* write protection */
192 #define MMU060_WE (0x00000010) /* bus error on write */
222 unsigned short wb3s; /* write back 3 status */
223 unsigned short wb2s; /* write back 2 status */
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| D | m53xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m53xxacr.h -- ColdFire version 3 core cache support
18 * configurable write-through or copy-back operation.
30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
31 #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
34 #define CACR_WPROTECT 0x00000020 /* Write protect*/
46 #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
47 #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
50 #define ACR_WPROTECT 0x00000004 /* Write protect region */
66 #define CACHE_WAYS 4 /* 4 ways - set associative */
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| /linux-6.12.1/arch/sh/include/asm/ |
| D | watchdog.h | 1 /* SPDX-License-Identifier: GPL-2.0+
3 * include/asm-sh/watchdog.h
25 * See cpu-sh2/watchdog.h for explanation of this stupidity..
36 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
39 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
42 * --------------------------------------------
63 * sh_wdt_read_cnt - Read from Counter
64 * Reads back the WTCNT value.
72 * sh_wdt_write_cnt - Write to Counter
73 * @val: Value to write
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| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac4_descs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
46 /* TDES3 (write back format) */
83 /* TDS3 use for both format (read and write back) */
89 /* RDES0 (write back format) */
92 /* RDES1 (write back format) */
107 /* RDES2 (write back format) */
121 /* RDES3 (write back format) */
144 /* TDS3 use for both format (read and write back) */
|
| /linux-6.12.1/drivers/comedi/drivers/ |
| D | pcl730.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Driver for Advantech PCL-730 and clones
10 * Description: Advantech PCL-730 (& compatibles)
11 * Devices: [Advantech] PCL-730 (pcl730), PCM-3730 (pcm3730), PCL-725 (pcl725),
12 * PCL-733 (pcl733), PCL-734 (pcl734),
13 * [ADLink] ACL-7130 (acl7130), ACL-7225b (acl7225b),
14 * [ICP] ISO-730 (iso730), P8R8-DIO (p8r8dio), P16R16-DIO (p16r16dio),
15 * [Diamond Systems] OPMM-1616-XT (opmm-1616-xt), PEARL-MM-P (pearl-mm-p),
16 * IR104-PBF (ir104-pbf),
21 * [0] - I/O port base
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| /linux-6.12.1/arch/sh/include/cpu-sh2/cpu/ |
| D | cache.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/cpu-sh2/cache.h
22 /* 0x00000000-0x7fffffff: Write-through */
23 /* 0x80000000-0x9fffffff: Write-back */
24 /* 0xc0000000-0xdfffffff: Write-through */
26 /* 0x00000000-0x7fffffff: Write-back */
27 /* 0x80000000-0x9fffffff: Write-through */
28 /* 0xc0000000-0xdfffffff: Write-back */
|
| /linux-6.12.1/Documentation/arch/x86/ |
| D | mtrr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Richard Gooch <rgooch@atnf.csiro.au> - 3 Jun 1999
8 - Luis R. Rodriguez <mcgrof@do-not-panic.com> - April 9, 2015
17 non-PAT systems while a no-op but equally effective on PAT enabled systems.
37 a video (VGA) card on a PCI or AGP bus. Enabling write-combining
38 allows bus write transfers to be combined into a larger transfer
40 of image write operations 2.5 times or more.
46 The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
50 The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. These
62 which allows you to read and write. The other is an ioctl()
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| /linux-6.12.1/drivers/infiniband/ulp/rtrs/ |
| D | README | 8 transport. It is optimized to transfer (read/write) IO blocks.
11 possibility to either write data from an sg list to the remote side
15 RTRS provides I/O fail-over and load-balancing capabilities by using
17 Documentation/ABI/testing/sysfs-class-rtrs-client).
26 --------
35 When processing an incoming write or read request, rtrs client uses memory
42 On an established session client sends to server write or read messages.
52 buffer after it returns back from the block layer and RNBD server.
53 The new rkey is sent back to the client along with the IO result.
64 ------------------------
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| /linux-6.12.1/include/linux/iio/ |
| D | backend.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 * IIO_BACKEND_EX_INFO - Helper for an IIO extended channel attribute
38 .write = iio_backend_ext_info_set, \
43 * struct iio_backend_data_fmt - Backend data format
72 * struct iio_backend_ops - operations structure for an iio_backend
91 * @debugfs_reg_access: Read or write register value of backend.
94 int (*enable)(struct iio_backend *back);
95 void (*disable)(struct iio_backend *back);
96 int (*chan_enable)(struct iio_backend *back, unsigned int chan);
97 int (*chan_disable)(struct iio_backend *back, unsigned int chan);
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| /linux-6.12.1/arch/arm/mm/ |
| D | cache-fa.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
19 #include "proc-macros.S"
70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
81 * - start - start address (inclusive, page aligned)
82 * - end - end address (exclusive, page aligned)
83 * - flags - vma_area_struct flags describing address space
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| D | cache.json | 23 …cess or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the …
27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.…
31 …counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to t…
39 …write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which ret…
43 …unts any full cache line write into the L2 cache which does not cause a linefill, including write-…
57 …unts any full cache line write into the L3 cache which does not cause a linefill, including write-…
67 …any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU.",
|
| /linux-6.12.1/arch/x86/lib/ |
| D | usercopy_64.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 * clean_cache_range - write back a cache range with CLWB
22 * @size: number of bytes to write back
24 * Write back a cache range using the CLWB (cache line write back)
31 unsigned long clflush_mask = x86_clflush_size - 1; in clean_cache_range()
56 * __copy_user_nocache() uses non-temporal stores for the bulk in __copy_user_flushcache()
60 * - Require 8-byte alignment when size is 8 bytes or larger. in __copy_user_flushcache()
61 * - Require 4-byte alignment when size is 4 bytes. in __copy_user_flushcache()
72 flushed = dest - (unsigned long) dst; in __copy_user_flushcache()
73 if (size > flushed && !IS_ALIGNED(size - flushed, 8)) in __copy_user_flushcache()
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| /linux-6.12.1/arch/arm/mach-omap2/ |
| D | sleep34xx.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
77 str r1, [r2, r3] @ write to l2dis_3630
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
96 dsb @ data write barrier
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
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| /linux-6.12.1/drivers/mmc/host/ |
| D | sdhci-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
43 struct mutex write_lock; /* protect back to back writes */
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
97 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_init()
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| /linux-6.12.1/arch/sh/mm/ |
| D | cache-sh2a.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2a.c
47 * Write back the dirty D-caches, but not invalidate them.
57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region()
59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
66 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { in sh2a__flush_wback_region()
89 * Write back the dirty D-caches and invalidate them.
97 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_purge_region()
98 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_purge_region()
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| D | cache-sh3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh3.c
23 * Write back the dirty D-caches, but not invalidate them.
38 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
39 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_wback_region()
40 & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
66 * Write back the dirty D-caches and invalidate them.
76 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
77 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_purge_region()
78 & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
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| D | cache-sh4.c | 2 * arch/sh/mm/cache-sh4.c
5 * Copyright (C) 2001 - 2009 Paul Mundt
35 * Write back the range of D-cache, and purge the I-cache.
47 start = data->addr1; in sh4_flush_icache_range()
48 end = data->addr2; in sh4_flush_icache_range()
51 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { in sh4_flush_icache_range()
57 * Selectively flush d-cache then invalidate the i-cache. in sh4_flush_icache_range()
60 start &= ~(L1_CACHE_BYTES-1); in sh4_flush_icache_range()
61 end += L1_CACHE_BYTES-1; in sh4_flush_icache_range()
62 end &= ~(L1_CACHE_BYTES-1); in sh4_flush_icache_range()
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| /linux-6.12.1/Documentation/w1/slaves/ |
| D | w1_therm.rst | 16 -----------
49 -1 if at least one sensor still in conversion, 1 if conversion is complete
60 adjust it (write). A temperature conversion time depends on the device type and
67 completion. Options 2, 3 can't be used in parasite power mode. To get back to
68 the default conversion time write ``0`` to ``conv_time``.
72 the sensor. Resolution is reset when the sensor gets power-cycled.
74 To store the current resolution in EEPROM, write ``0`` to ``w1_slave``.
81 Some non-genuine DS18B20 chips are fixed in 12-bit mode only, so the actual
82 resolution is read back from the chip and verified.
86 The write-only sysfs entry ``eeprom_cmd`` is an alternative for EEPROM operations.
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