| /linux-6.12.1/Documentation/devicetree/bindings/watchdog/ |
| D | linux,wdt-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
18 description: gpio connection to WDT reset pin
24 - description:
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| D | men-a021-wdt.txt | 1 Bindings for MEN A21 Watchdog device connected to GPIO lines
4 - compatible: "men,a021-wdt"
5 - gpios: Specifies the pins that control the Watchdog, order:
7 2: Watchdog fast-mode
14 - None
18 compatible ="men,a021-wdt";
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| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt7620-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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| D | mediatek,mt7621-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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| D | mediatek,mt76x8-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt76x8-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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| /linux-6.12.1/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_gpt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * for GPIO or can be used to raise interrupts. The timer function can
14 * This driver supports the GPIO and IRQ controller functions of the GPT
17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
24 * To use the GPIO function, the following two properties must be added
27 * gpio-controller;
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
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| D | mpc52xx_common.c | 25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
81 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
110 { .compatible = "fsl,mpc5200-gpt", },
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
45 device-width = <2>;
46 #address-cells = <1>;
47 #size-cells = <1>;
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| D | ge_imp3a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
51 #address-cells = <1>;
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| D | gef_sbc310.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
48 read-only;
54 compatible = "gef,sbc310-paged-flash", "cfi-flash";
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| D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
45 device-width = <2>;
46 #address-cells = <1>;
47 #size-cells = <1>;
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| /linux-6.12.1/Documentation/devicetree/bindings/mfd/ |
| D | kontron,sl28cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
38 interrupt-controller: true
41 "^gpio(@[0-9a-f]+)?$":
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| /linux-6.12.1/arch/arm/boot/dts/synaptics/ |
| D | berlin2cd.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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| /linux-6.12.1/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
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| /linux-6.12.1/arch/arm/boot/dts/ti/keystone/ |
| D | keystone.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
31 compatible = "arm,gic-400", "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
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| /linux-6.12.1/drivers/watchdog/ |
| D | bd9576_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/consumer.h>
10 #include <linux/mfd/rohm-bd957x.h>
37 gpiod_set_value_cansleep(priv->gpiod_en, 0); in bd9576_wdt_disable()
45 gpiod_set_value_cansleep(priv->gpiod_ping, 1); in bd9576_wdt_ping()
46 gpiod_set_value_cansleep(priv->gpiod_ping, 0); in bd9576_wdt_ping()
55 gpiod_set_value_cansleep(priv->gpiod_en, 1); in bd9576_wdt_start()
97 return -EINVAL; in find_closest_fast()
113 return -EINVAL; in find_closest_slow_by_fast()
141 return -EINVAL; in find_closest_slow()
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| D | mena21_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/gpio/consumer.h>
33 struct watchdog_device wdt; member
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
53 static int a21_wdt_start(struct watchdog_device *wdt) in a21_wdt_start() argument
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start()
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
62 static int a21_wdt_stop(struct watchdog_device *wdt) in a21_wdt_stop() argument
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| D | mtx-1_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for the MTX-1 Watchdog.
5 * (C) Copyright 2005 4G Systems <info@4g-systems.biz>,
7 * http://www.4g-systems.biz
10 * (c) Copyright 2005 4G Systems <info@4g-systems.biz>
13 * Author: Michael Stickel michael.stickel@4g-systems.biz
19 * The Watchdog is configured to reset the MTX-1
42 #include <linux/gpio/consumer.h>
64 ticks--; in mtx1_wdt_trigger()
66 /* toggle wdt gpio */ in mtx1_wdt_trigger()
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| D | gpio_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for watchdog device controlled through GPIO-line
10 #include <linux/gpio/consumer.h>
42 gpiod_set_value_cansleep(priv->gpiod, 1); in gpio_wdt_disable()
44 /* Put GPIO back to tristate */ in gpio_wdt_disable()
45 if (priv->hw_algo == HW_ALGO_TOGGLE) in gpio_wdt_disable()
46 gpiod_direction_input(priv->gpiod); in gpio_wdt_disable()
53 switch (priv->hw_algo) { in gpio_wdt_ping()
56 priv->state = !priv->state; in gpio_wdt_ping()
57 gpiod_set_value_cansleep(priv->gpiod, priv->state); in gpio_wdt_ping()
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| /linux-6.12.1/arch/arm64/boot/dts/synaptics/ |
| D | berlin4ct.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
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| /linux-6.12.1/drivers/pinctrl/mediatek/ |
| D | pinctrl-mt7620.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
73 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
74 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
75 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
78 FUNC("wdt rst", 0, 17, 1),
79 FUNC("wdt refclk", 0, 17, 1),
96 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
119 { .compatible = "ralink,mt7620-pinctrl" },
120 { .compatible = "ralink,rt2880-pinmux" },
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| /linux-6.12.1/drivers/mfd/ |
| D | rdc321x-southbridge.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007-2010 Florian Fainelli <florian@openwrt.org>
19 .name = "wdt-reg",
32 .name = "gpio-reg1",
37 .name = "gpio-reg2",
46 .name = "rdc321x-wdt",
52 .name = "rdc321x-gpio",
67 dev_err(&pdev->dev, "failed to enable device\n"); in rdc321x_sb_probe()
74 return devm_mfd_add_devices(&pdev->dev, -1, in rdc321x_sb_probe()
96 MODULE_DESCRIPTION("RDC R-321x MFD southbridge driver");
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| /linux-6.12.1/Documentation/devicetree/bindings/firmware/ |
| D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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| /linux-6.12.1/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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