powerpc/fsl/mpc5200.txt

2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>].  The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 	compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35     ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s".  This convention is chosen to
40 avoid naming conflicts with non-psc devices providing the same
41 function.  For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
48 ------------
55 ----			-----------
59 compatible		mpc5200: "fsl,mpc5200-immr"
60 			mpc5200b: "fsl,mpc5200b-immr"
61 system-frequency	'fsystem' frequency in Hz; XLB, IPB, USB and PCI
63 bus-frequency		IPB bus frequency in Hz.  Clock rate
67 ---------------
71 tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
75 ----				----------		-----------
76 cdm@<addr>			fsl,mpc5200-cdm		Clock Distribution
77 interrupt-controller@<addr>	fsl,mpc5200-pic		need an interrupt
79 bestcomm@<addr>			fsl,mpc5200-bestcomm	Bestcomm DMA controller
83 ----		----------		-----------
84 timer@<addr>	fsl,mpc5200-gpt		 General purpose timers
85 gpio@<addr>	fsl,mpc5200-gpio	 MPC5200 simple gpio controller
86 gpio@<addr>	fsl,mpc5200-gpio-wkup	 MPC5200 wakeup gpio controller
87 rtc@<addr>	fsl,mpc5200-rtc		 Real time clock
88 mscan@<addr>	fsl,mpc5200-mscan	 CAN bus controller
89 pci@<addr>	fsl,mpc5200-pci		 PCI bridge
90 serial@<addr>	fsl,mpc5200-psc-uart	 PSC in serial mode
91 i2s@<addr>	fsl,mpc5200-psc-i2s	 PSC in i2s mode
92 ac97@<addr>	fsl,mpc5200-psc-ac97	 PSC in ac97 mode
93 spi@<addr>	fsl,mpc5200-psc-spi	 PSC in spi mode
94 irda@<addr>	fsl,mpc5200-psc-irda	 PSC in IrDA mode
95 spi@<addr>	fsl,mpc5200-spi		 MPC5200 spi device
96 ethernet@<addr>	fsl,mpc5200-fec		 MPC5200 ethernet device
97 ata@<addr>	fsl,mpc5200-ata		 IDE ATA interface
98 i2c@<addr>	fsl,mpc5200-i2c		 I2C controller
99 usb@<addr>	fsl,mpc5200-ohci,ohci-be USB controller
100 xlb@<addr>	fsl,mpc5200-xlb		 XLB arbitrator
102 fsl,mpc5200-gpt nodes
103 ---------------------
105 design supports the internal wdt, then the device node for GPT0 should
106 include the empty property 'fsl,has-wdt'.  Note that this does not activate
110 gpt api call to this timer will fail with -EBUSY.
113 	fsl,wdt-on-boot = <n>;
114 GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
117 - just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
118 - do not touch a configuration assigned by the boot loader which supervises
123 An mpc5200-gpt can be used as a single line GPIO controller.  To do so,
125 	gpio-controller;
126 	#gpio-cells = <2>;
127 When referencing the GPIO line from another node, the first cell must always
128 be zero and the second cell represents the gpio flags and described in the
129 gpio device tree binding.
131 An mpc5200-gpt can be used as a single line edge sensitive interrupt
133 	interrupt-controller;
134 	#interrupt-cells = <1>;
138 fsl,mpc5200-psc nodes
139 ---------------------
140 The PSCs should include a cell-index which is the index of the PSC in
141 hardware.  cell-index is used to determine which shared SoC registers to
142 use when setting up PSC clocking.  cell-index number starts at '0'.  ie:
143 	PSC1 has 'cell-index = <0>'
144 	PSC4 has 'cell-index = <3>'
147 i2s mode.  An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
151 fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
152 ------------------------------------------------
153 Each GPIO controller node should have the empty property gpio-controller and
154 #gpio-cells set to 2. First cell is the GPIO number which is interpreted
155 according to the bit numbers in the GPIO control registers. The second cell
158 fsl,mpc5200-fec nodes
159 ---------------------
162 - fsl,7-wire-mode - An empty property that specifies the link uses 7-wire
164 - current-speed   - Specifies that the MII should be configured for a fixed
168 - phy-handle      - Contains a phandle to an Ethernet PHY.
170 Interrupt controller (fsl,mpc5200-pic) node
171 -------------------------------------------
196 fsl,mpc5200-mscan nodes
197 -----------------------