| /linux-6.12.1/drivers/clk/meson/ |
| D | vclk.c | 7 #include "vclk.h"
9 /* The VCLK gate has a supplementary reset bit to pulse after ungating */
20 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_enable() local
22 meson_parm_write(clk->map, &vclk->enable, 1); in meson_vclk_gate_enable()
25 meson_parm_write(clk->map, &vclk->reset, 1); in meson_vclk_gate_enable()
26 meson_parm_write(clk->map, &vclk->reset, 0); in meson_vclk_gate_enable()
34 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_disable() local
36 meson_parm_write(clk->map, &vclk->enable, 0); in meson_vclk_gate_disable()
42 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_is_enabled() local
44 return meson_parm_read(clk->map, &vclk->enable); in meson_vclk_gate_is_enabled()
[all …]
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| D | vclk.h | 15 * @enable: vclk enable field
16 * @reset: vclk reset field
34 * @enable: vclk divider enable field
35 * @reset: vclk divider reset field
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 932 * @vclk: wanted VCLK
942 * @optimal_vclk_div: resulting vclk post divider
949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
978 /* calc vclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
979 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | sumo_dpm.c | 822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
838 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
856 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1412 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1415 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| /linux-6.12.1/drivers/gpu/drm/renesas/rz-du/ |
| D | rzg2l_mipi_dsi.c | 41 struct clk *vclk; member
273 * Relationship between hsclk and vclk must follow in rzg2l_mipi_dsi_startup()
274 * vclk * bpp = hsclk * 8 * lanes in rzg2l_mipi_dsi_startup()
275 * where vclk: video clock (Hz) in rzg2l_mipi_dsi_startup()
289 clk_set_rate(dsi->vclk, mode->clock * 1000); in rzg2l_mipi_dsi_startup()
722 dsi->vclk = devm_clk_get(dsi->dev, "vclk"); in rzg2l_mipi_dsi_probe()
723 if (IS_ERR(dsi->vclk)) in rzg2l_mipi_dsi_probe()
724 return PTR_ERR(dsi->vclk); in rzg2l_mipi_dsi_probe()
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | aspeed-video.txt | 13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
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| /linux-6.12.1/drivers/video/fbdev/nvidia/ |
| D | nv_hw.c | 380 static void nv4UpdateArbitrationSettings(unsigned VClk, in nv4UpdateArbitrationSettings() argument
402 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
618 static void nv10UpdateArbitrationSettings(unsigned VClk, in nv10UpdateArbitrationSettings() argument
642 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
676 static void nForceUpdateArbitrationSettings(unsigned VClk, in nForceUpdateArbitrationSettings() argument
744 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
771 unsigned VClk, Freq; in CalcVClock() local
776 VClk = (unsigned)clockIn; in CalcVClock()
787 Freq = VClk << P; in CalcVClock()
790 N = ((VClk << P) * M) / par->CrystalFreqKHz; in CalcVClock()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,fimd.yaml | 46 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
119 samsung,invert-vclk:
185 samsung,invert-vclk;
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| /linux-6.12.1/drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 50 struct clk *vclk; member
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
723 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
724 if (IS_ERR(ctx->vclk)) { in decon_probe()
726 ret = PTR_ERR(ctx->vclk); in decon_probe()
783 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
817 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
819 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n", in exynos7_decon_resume()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 193 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, in nv04_update_arb() argument
205 sim_data.pclk_khz = VClk; in nv04_update_arb()
252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| /linux-6.12.1/drivers/video/fbdev/via/ |
| D | vt1636.c | 186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| /linux-6.12.1/drivers/media/platform/renesas/rzg2l-cru/ |
| D | rzg2l-csi2.c | 111 struct clk *vclk; member
390 clk_disable_unprepare(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
395 return clk_prepare_enable(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
767 csi2->vclk = devm_clk_get(&pdev->dev, "video"); in rzg2l_csi2_probe()
768 if (IS_ERR(csi2->vclk)) in rzg2l_csi2_probe()
769 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->vclk), in rzg2l_csi2_probe()
771 csi2->vclk_rate = clk_get_rate(csi2->vclk); in rzg2l_csi2_probe()
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| D | rzg2l-cru.h | 69 * @vclk: CRU Main clock
106 struct clk *vclk; member
|
| /linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_5_ppsmc.h | 52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | renesas,rzg2l-du.yaml | 44 - const: vclk
130 clock-names = "aclk", "pclk", "vclk";
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| D | xylon,logicvc-display.yaml | 45 # vclk is required and must be provided as first item.
46 - const: vclk
228 clock-names = "vclk", "lvdsclk";
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| /linux-6.12.1/drivers/tty/serial/8250/ |
| D | 8250_aspeed_vuart.c | 424 struct clk *vclk; in aspeed_vuart_probe() local
464 vclk = devm_clk_get_enabled(dev, NULL); in aspeed_vuart_probe()
465 if (IS_ERR(vclk)) { in aspeed_vuart_probe()
466 rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n"); in aspeed_vuart_probe()
470 port.port.uartclk = clk_get_rate(vclk); in aspeed_vuart_probe()
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| /linux-6.12.1/drivers/video/fbdev/riva/ |
| D | riva_hw.c | 609 unsigned VClk, in nv3UpdateArbitrationSettings() argument
635 sim_data.pclk_khz = VClk; in nv3UpdateArbitrationSettings()
793 unsigned VClk, in nv4UpdateArbitrationSettings() argument
820 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
1042 unsigned VClk, in nv10UpdateArbitrationSettings() argument
1071 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
1087 unsigned VClk, in nForceUpdateArbitrationSettings() argument
1127 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
1162 unsigned VClk, Freq; in CalcVClock() local
1167 VClk = (unsigned)clockIn; in CalcVClock()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | power_state.h | 144 uint32_t VCLK; member
184 unsigned long vclk; member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | dcn301_smu.h | 38 uint32_t vclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
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| /linux-6.12.1/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 73 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
90 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
216 printk(KERN_CRIT "atyfb: vclk out of range\n"); in aty_valid_pll_ct()
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", in aty_valid_pll_ct()
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ in aty_valid_pll_ct()
314 /* Reset VCLK generator */ in aty_set_pll_ct()
337 /* End VCLK generator reset */ in aty_set_pll_ct()
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| /linux-6.12.1/arch/arm64/boot/dts/renesas/ |
| D | r9a07g043u.dtsi | 139 clock-names = "aclk", "pclk", "vclk";
151 clock-names = "aclk", "pclk", "vclk";
163 clock-names = "aclk", "pclk", "vclk";
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| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dsi.yaml | 66 - const: vclk
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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| /linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu8_hwmgr.c | 140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
600 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
602 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1438 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1746 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1780 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1781 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1916 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
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