7 #include "vclk.h"
9 /* The VCLK gate has a supplementary reset bit to pulse after ungating */
20 	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);  in meson_vclk_gate_enable()  local
22 	meson_parm_write(clk->map, &vclk->enable, 1);  in meson_vclk_gate_enable()
25 	meson_parm_write(clk->map, &vclk->reset, 1);  in meson_vclk_gate_enable()
26 	meson_parm_write(clk->map, &vclk->reset, 0);  in meson_vclk_gate_enable()
34 	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);  in meson_vclk_gate_disable()  local
36 	meson_parm_write(clk->map, &vclk->enable, 0);  in meson_vclk_gate_disable()
42 	struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);  in meson_vclk_gate_is_enabled()  local
44 	return meson_parm_read(clk->map, &vclk->enable);  in meson_vclk_gate_is_enabled()
54 /* The VCLK Divider has supplementary reset & enable bits */
66 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_recalc_rate()  local
68 	return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),  in meson_vclk_div_recalc_rate()
69 				   vclk->table, vclk->flags, vclk->div.width);  in meson_vclk_div_recalc_rate()
76 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_determine_rate()  local
78 	return divider_determine_rate(hw, req, vclk->table, vclk->div.width,  in meson_vclk_div_determine_rate()
79 				      vclk->flags);  in meson_vclk_div_determine_rate()
86 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_set_rate()  local
89 	ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,  in meson_vclk_div_set_rate()
90 			      vclk->flags);  in meson_vclk_div_set_rate()
94 	meson_parm_write(clk->map, &vclk->div, ret);  in meson_vclk_div_set_rate()
102 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_enable()  local
105 	meson_parm_write(clk->map, &vclk->reset, 0);  in meson_vclk_div_enable()
106 	meson_parm_write(clk->map, &vclk->enable, 1);  in meson_vclk_div_enable()
114 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_disable()  local
117 	meson_parm_write(clk->map, &vclk->enable, 0);  in meson_vclk_div_disable()
118 	meson_parm_write(clk->map, &vclk->reset, 1);  in meson_vclk_div_disable()
124 	struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);  in meson_vclk_div_is_enabled()  local
126 	return meson_parm_read(clk->map, &vclk->enable);  in meson_vclk_div_is_enabled()
139 MODULE_DESCRIPTION("Amlogic vclk clock driver");