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/linux-6.12.1/net/netlabel/
Dnetlabel_addrlist.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
27 * struct netlbl_af4list - NetLabel IPv4 address list
29 * @mask: IPv4 address mask
30 * @valid: valid flag
35 __be32 mask; member
37 u32 valid; member
42 * struct netlbl_af6list - NetLabel IPv6 address list
44 * @mask: IPv6 address mask
[all …]
Dnetlabel_addrlist.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
59 * netlbl_af4list_search_exact - Search for an exact IPv4 address entry
61 * @mask: IPv4 address mask
71 __be32 mask, in netlbl_af4list_search_exact() argument
77 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
86 * netlbl_af6list_search - Search for a matching IPv6 address entry
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Darm,vic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
[all …]
Darm,versatile-fpga-irq.txt9 - compatible: "arm,versatile-fpga-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
18 the interrupts are valid. Unconnected/unused lines are set to 0, and
22 The "oxsemi,ox810se-rps-irq" compatible is deprecated.
27 compatible = "arm,versatile-fpga-irq";
28 #interrupt-cells = <1>;
[all …]
/linux-6.12.1/drivers/net/ethernet/apm/xgene/
Dxgene_enet_cle.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Classifier structures
27 if (pdata->enet_id == XGENE_ENET1) { in xgene_cle_idt_to_hw()
41 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
42 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) | in xgene_cle_dbptr_to_hw()
43 SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) | in xgene_cle_dbptr_to_hw()
44 SET_VAL(CLE_DSTQIDL, dbptr->dstqid); in xgene_cle_dbptr_to_hw()
46 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) | in xgene_cle_dbptr_to_hw()
47 SET_VAL(CLE_PRIORITY, dbptr->cle_priority); in xgene_cle_dbptr_to_hw()
55 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type); in xgene_cle_kn_to_hw()
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/prestera/
Dprestera_flower.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
19 prestera_acl_ruleset_put(template->ruleset); in prestera_flower_template_free()
20 list_del(&template->list); in prestera_flower_template_free()
29 list_for_each_entry_safe(template, tmp, &block->template_list, list) in prestera_flower_template_cleanup()
41 if (act->chain_index <= chain_index) in prestera_flower_parse_goto_action()
43 return -EINVAL; in prestera_flower_parse_goto_action()
45 if (rule->re_arg.jump.valid) in prestera_flower_parse_goto_action()
46 return -EEXIST; in prestera_flower_parse_goto_action()
48 ruleset = prestera_acl_ruleset_get(block->sw->acl, block, in prestera_flower_parse_goto_action()
49 act->chain_index); in prestera_flower_parse_goto_action()
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
38 * @valid: mask for valid IRQs on this controller
43 u32 valid; member
55 u32 mask = 1 << d->hwirq; in fpga_irq_mask() local
57 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
63 u32 mask = 1 << d->hwirq; in fpga_irq_unmask() local
65 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
72 seq_printf(p, irq_domain_get_of_node(f->domain)->name); in fpga_irq_print_chip()
[all …]
/linux-6.12.1/drivers/net/ethernet/aquantia/atlantic/macsec/
Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
68 /*! This is to specify the 40bit SNAP header if the SNAP header's mask
72 /*! This is to specify the 24bit LLC header if the LLC header's mask is
122 /*! Mask is per-byte.
132 * 1: enable comparison of extracted VLAN Valid field.
135 /*! This is bit mask to enable comparison the 8 bit TCI field,
142 /*! Mask is per-byte.
151 /*! Mask is per-byte.
156 /*! Mask is per-byte.
[all …]
/linux-6.12.1/arch/x86/events/amd/
Dlbr.c1 // SPDX-License-Identifier: GPL-2.0
7 /* LBR Branch Select valid bits */
33 #define LBR_NOT_SUPP -1 /* unsupported filter */
56 u64 valid:1; member
92 u32 shift = 64 - boot_cpu_data.x86_virt_bits; in sign_ext_branch_ip()
100 int br_sel = cpuc->br_sel, offset, type, i, j; in amd_pmu_lbr_filter()
110 for (i = 0; i < cpuc->lbr_stack.nr; i++) { in amd_pmu_lbr_filter()
111 from = cpuc->lbr_entries[i].from; in amd_pmu_lbr_filter()
112 to = cpuc->lbr_entries[i].to; in amd_pmu_lbr_filter()
121 cpuc->lbr_entries[i].from += offset; in amd_pmu_lbr_filter()
[all …]
/linux-6.12.1/drivers/net/ethernet/pensando/ionic/
Dionic_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
9 /** struct ionic_intr - interrupt control register set.
11 * @mask: interrupt mask value.
13 * @mask_assert: interrupt mask value on assert.
18 u32 mask; member
28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
30 * @IONIC_INTR_MASK_SET: mask interrupt.
37 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Ds3c6400.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
33 clocks: clock-controller@7e00f000 {
34 compatible = "samsung,s3c6400-clock";
36 #clock-cells = <1>;
Ds3c6410.dtsi1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
[all …]
/linux-6.12.1/drivers/net/ipa/
Dipa_smp2p.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2024 Linaro Ltd.
35 * whether power is enabled using two SMP2P state bits--one to indicate
37 * bit is valid. The modem will poll the valid bit until it is set, and
45 * struct ipa_smp2p - IPA SMP2P information
47 * @valid_state: SMEM state indicating enabled state is valid
49 * @valid_bit: Valid bit in 32-bit SMEM state mask
50 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
51 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
[all …]
/linux-6.12.1/include/linux/
Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
54 #define REGMAP_UPSHIFT(s) (-(s))
66 * struct reg_default - Default value for a register.
80 * struct reg_sequence - An individual write from a sequence of writes.
103 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
110 * tight-loops). Should be less than ~20ms since usleep_range
111 * is used (see Documentation/timers/timers-howto.rst).
114 * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
130 * regmap_read_poll_timeout_atomic - Poll until a condition is met or a timeout occurs
136 * @delay_us: Time to udelay between reads in us (0 tight-loops).
[all …]
/linux-6.12.1/drivers/net/phy/
Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
145 bool valid; member
[all …]
/linux-6.12.1/drivers/firmware/imx/
Dimx-scu-irq.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/firmware/imx/rsrc.h>
40 u32 mask; member
47 u32 mask; member
49 bool valid; member
91 if (scu_irq_wakeup[i].mask) { in imx_scu_irq_work_handler()
92 scu_irq_wakeup[i].valid = false; in imx_scu_irq_work_handler()
105 if (scu_irq_wakeup[i].mask & irq_status) { in imx_scu_irq_work_handler()
106 scu_irq_wakeup[i].valid = true; in imx_scu_irq_work_handler()
107 scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask; in imx_scu_irq_work_handler()
[all …]
/linux-6.12.1/arch/arm/mach-pxa/
Dmfp-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
13 #include <linux/gpio-pxa.h>
21 #include "pxa2xx-regs.h"
22 #include "mfp-pxa2xx.h"
23 #include "mfp-pxa27x.h"
32 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
41 unsigned valid : 1; member
45 unsigned int mask; /* bit mask in PWER or PKWR */ member
46 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
24 * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
35 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
36 * @i2c_mcode_mask: MCODE field mask for I2C config register
39 * XXX VALID should probably be a shift, not a mask
43 u32 valid; member
63 * struct omap_vc_channel - VC per-instance data
69 * @i2c_high_speed: whether or not to use I2C high-speed mode
[all …]
/linux-6.12.1/drivers/misc/cxl/
Dhcalls.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 * The 'flags' parameter regroups the various bit-fields
59 * cxl_h_detach_process - Detach a process element from a coherent
65 * cxl_h_reset_afu - Perform a reset to the coherent platform function.
70 * cxl_h_suspend_process - Suspend a process from being executed
71 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
77 * cxl_h_resume_process - Resume a process to be executed
78 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
84 * cxl_h_read_error_state - Reads the error state of the coherent
91 * cxl_h_get_afu_err - collect the AFU error buffer
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Ddavinci-nand.txt7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
23 Can be in the range [0-3].
27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
[all …]
/linux-6.12.1/fs/nfsd/
Dnfs4acl.c68 int mask = NFS4_ANYONE_MODE; in mask_from_posix() local
71 mask |= NFS4_OWNER_MODE; in mask_from_posix()
73 mask |= NFS4_READ_MODE; in mask_from_posix()
75 mask |= NFS4_WRITE_MODE; in mask_from_posix()
77 mask |= NFS4_ACE_DELETE_CHILD; in mask_from_posix()
79 mask |= NFS4_EXECUTE_MODE; in mask_from_posix()
80 return mask; in mask_from_posix()
86 u32 mask = 0; in deny_mask_from_posix() local
89 mask |= NFS4_READ_MODE; in deny_mask_from_posix()
91 mask |= NFS4_WRITE_MODE; in deny_mask_from_posix()
[all …]
/linux-6.12.1/rust/kernel/net/
Dphy.rs1 // SPDX-License-Identifier: GPL-2.0
45 /// PHY is in full-duplex mode.
47 /// PHY is in half-duplex mode.
62 /// - Referencing a `phy_device` using this struct asserts that you are in
64 /// - This struct always has a valid `self.0.mdio.dev`.
82 /// - the pointer must point at a valid `phy_device`, and the caller
85 /// - `(*ptr).mdio.dev` must be a valid.
86 unsafe fn from_raw<'a>(ptr: *mut bindings::phy_device) -> &'a mut Self { in from_raw()
89 // SAFETY: by the function requirements the pointer is valid and we have unique access for in from_raw()
95 pub fn phy_id(&self) -> u32 { in phy_id()
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_tc_lib.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2019-2021, Intel Corporation. */
71 __be16 vlan_id; /* Only last 12 bits valid */
72 __be16 vlan_prio; /* Only last 3 bits valid (valid values: 0..7) */
120 /* L2 layer fields with their mask */
127 /* L3 (IPv4[6]) layer fields with their mask */
131 /* L4 layer fields with their mask */
181 * ice_is_chnl_fltr - is this a valid channel filter
182 * @f: Pointer to tc-flower filter
184 * Criteria to determine of given filter is valid channel filter
[all …]
/linux-6.12.1/drivers/memory/
Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct emif_data - Per device static data for driver's use
38 * to this EMIF - read from MR4 register. If there
43 * @base: base address of memory-mapped IO registers.
47 * frequencies, to avoid re-calculating them on
77 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
78 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
81 regs->freq/1000000); in do_emif_regdump_show()
83 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
84 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); in do_emif_regdump_show()
[all …]

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