| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
[all …]
|
| D | socionext,uniphier-usb3ss-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
[all …]
|
| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| D | renesas,usb3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
|
| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/nvidia/ |
| D | tegra234-p3740-0002+p3701-0008.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
29 dai-format = "i2s";
30 remote-endpoint = <&rt5640_ep>;
[all …]
|
| D | tegra234-p3737-0000+p3701-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
8 #include "tegra234-p3701-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
21 stdout-path = "serial0:115200n8";
31 dai-format = "i2s";
32 remote-endpoint = <&rt5640_ep>;
[all …]
|
| D | tegra234-p3768-0000+p3767.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
|
| D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
|
| D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
[all …]
|
| D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
[all …]
|
| D | nvidia,tegra234-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
20 const: nvidia,tegra234-xusb
24 - description: xHCI host registers
25 - description: XUSB FPCI registers
[all …]
|
| D | cdns,usb3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller
10 - Pawel Laszczak <pawell@cadence.com>
14 const: cdns,usb3
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
[all …]
|
| /linux-6.12.1/drivers/usb/dwc3/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
64 AM437x use this IP for USB2/3 functionality.
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
78 tristate "PCIe-based Platforms"
86 tristate "Synopsys PCIe-based HAPS Platforms"
98 Support of USB2/3 functionality in TI Keystone2 and AM654 platforms.
109 Support USB2/3 functionality in Amlogic G12A platforms.
117 Support USB2/3 functionality in simple SoC integrations.
[all …]
|
| /linux-6.12.1/fs/ufs/ |
| D | util.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 return &cpi->c_ubh; in UCPI_UBH()
23 return &spi->s_ubh; in USPI_UBH()
33 struct ufs_super_block_third *usb3) in ufs_get_fs_state() argument
35 switch (UFS_SB(sb)->s_flags & UFS_ST_MASK) { in ufs_get_fs_state()
37 if (fs32_to_cpu(sb, usb3->fs_postblformat) == UFS_42POSTBLFMT) in ufs_get_fs_state()
38 return fs32_to_cpu(sb, usb1->fs_u0.fs_sun.fs_state); in ufs_get_fs_state()
41 return fs32_to_cpu(sb, usb3->fs_un2.fs_sun.fs_state); in ufs_get_fs_state()
43 return fs32_to_cpu(sb, usb1->fs_u1.fs_sunx86.fs_state); in ufs_get_fs_state()
46 return fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_state); in ufs_get_fs_state()
[all …]
|
| D | super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * Laboratoire MASI - Institut Blaise Pascal
25 * Big-endian to little-endian byte-swapping/bitmaps by
35 * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu)
48 * Francois-Rene Rideau <fare@tunes.org>
52 * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>.
84 #include <linux/backing-dev.h>
101 struct ufs_sb_private_info *uspi = UFS_SB(sb)->s_uspi; in ufs_nfs_get_inode()
104 if (ino < UFS_ROOTINO || ino > (u64)uspi->s_ncg * uspi->s_ipg) in ufs_nfs_get_inode()
105 return ERR_PTR(-ESTALE); in ufs_nfs_get_inode()
[all …]
|
| /linux-6.12.1/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
100 #define HSIC_PD_TX_STROBE BIT(3)
129 #define CLR_WAKE_ALARM BIT(3)
133 #define HSIC_CLR_WAKE_ALARM BIT(3)
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
16 3 ge1 Gigabit Ethernet 1
29 -----------------------------------
31 3 pp Packet Processor
39 16 usb3 USB3 Host
56 -----------------------------------
59 3 ge1 Gigabit Ethernet 1
63 7 pex3 PCIe 3
65 9 usb3h0 USB3 Host 0
66 10 usb3h1 USB3 Host 1
[all …]
|
| /linux-6.12.1/drivers/usb/gadget/udc/ |
| D | renesas_usb3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB3.0 Peripheral driver (USB gadget)
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
13 #include <linux/extcon-provider.h>
37 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
38 #define USB3_DMA_CH0_PRD_ADR(n) (0x034 + ((n) - 1) * 0x10) /* n = 1 to 4 */
43 #define USB3_DRD_CON(p) ((p)->is_rzv2m ? 0x400 : 0x218)
50 #define USB3_USB_OTG_STA(p) ((p)->is_rzv2m ? 0x410 : 0x268)
51 #define USB3_USB_OTG_INT_STA(p) ((p)->is_rzv2m ? 0x414 : 0x26c)
[all …]
|
| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-388-clearfog.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
[all …]
|
| /linux-6.12.1/drivers/phy/socionext/ |
| D | phy-uniphier-usb3ss.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
34 #define CDR_CPD_TRIM PHY_F(7, 3, 0) /* RxPLL charge pump current */
35 #define CDR_CPF_TRIM PHY_F(8, 3, 0) /* RxPLL charge pump current 2 */
36 #define TX_PLL_TRIM PHY_F(9, 3, 0) /* TxPLL charge pump current */
37 #define BGAP_TRIM PHY_F(11, 3, 0) /* Bandgap voltage */
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
[all …]
|
| /linux-6.12.1/Documentation/driver-api/usb/ |
| D | usb3-debug-port.rst | 2 USB3 debug port
11 This is a HOWTO for using the USB3 debug port on x86 systems.
13 Before using any kernel debugging functionality based on USB3
16 1) check whether any USB3 debug port is available in
19 3) have a USB 3.0 super-speed A-to-A debugging cable.
29 device through the debug port (normally the first USB3
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | armada-3720-espressobin-ultra.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for ESPRESSObin-Ultra board.
9 /dts-v1/;
11 #include "armada-3720-espressobin.dtsi"
15 compatible = "globalscale,espressobin-ultra", "globalscale,espressobin",
27 /delete-node/ regulator;
29 reg_usb3_vbus: usb3-vbus {
30 compatible = "regulator-fixed";
31 regulator-name = "usb3-vbus";
32 regulator-min-microvolt = <5000000>;
[all …]
|