bindings/clock/mvebu-gated-clock.txt

12 -----------------------------------
16 3	ge1	Gigabit Ethernet 1
29 -----------------------------------
31 3	pp		Packet Processor
39 16	usb3		USB3 Host
56 -----------------------------------
59 3	ge1		Gigabit Ethernet 1
63 7	pex3		PCIe 3
65 9	usb3h0		USB3 Host 0
66 10	usb3h1		USB3 Host 1
67 11	usb3d		USB3 Device
83 -----------------------------------
86 7	pex3		PCIe 3
88 9	usb3h0		USB3 Host 0
89 10	usb3h1		USB3 Host 1
97 -----------------------------------
99 1	ge3	Gigabit Ethernet 3
101 3	ge1	Gigabit Ethernet 1
106 8	pex3	PCIe Cntrl 3
124 -----------------------------------
125 3	ge1	Gigabit Ethernet 1
134 -----------------------------------
138 3	sata	SATA Host
157 -----------------------------------
160 3	usb0	USB Host 0
176 - compatible : shall be one of the following:
177 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 	"marvell,dove-gating-clock" - for Dove SoC clock gating
184 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
186 - #clock-cells : from common clock binding; shall be set to 1
189 - clocks : default parent clock phandle (e.g. tclk)
193 gate_clk: clock-gating-control@d0038 {
194 	compatible = "marvell,dove-gating-clock";
198 	#clock-cells = <1>;
202 	compatible = "marvell,dove-sdhci";