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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
Dnvidia,tegra234-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
20 const: nvidia,tegra234-xusb
24 - description: xHCI host registers
25 - description: XUSB FPCI registers
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra234-p3740-0002+p3701-0008.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
29 dai-format = "i2s";
30 remote-endpoint = <&rt5640_ep>;
[all …]
Dtegra234-p3737-0000+p3701-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
8 #include "tegra234-p3701-0000.dtsi"
12 compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
21 stdout-path = "serial0:115200n8";
31 dai-format = "i2s";
32 remote-endpoint = <&rt5640_ep>;
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Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
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Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drenesas,usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,usb2-phy-r8a77470 # RZ/G1C
18 - renesas,usb2-phy-r9a08g045 # RZ/G3S
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Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB2 PHY
11 USB2 controller implemented on Socionext UniPhier SoCs.
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
Dsamsung,usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
18 0 - USB device ("device"),
19 1 - USB host ("host"),
20 2 - HSIC0 ("hsic0"),
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux-6.12.1/drivers/phy/tegra/
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
100 #define HSIC_PD_TX_STROBE BIT(3)
129 #define CLR_WAKE_ALARM BIT(3)
133 #define HSIC_CLR_WAKE_ALARM BIT(3)
[all …]
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
126 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
157 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TRX (1 << 3)
179 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
207 u32 hs_curr_level[3];
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
[all …]
/linux-6.12.1/drivers/phy/broadcom/
Dphy-bcm-ns-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
34 struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy); in bcm_ns_usb2_phy_init() local
35 struct device *dev = usb2->dev; in bcm_ns_usb2_phy_init()
39 err = clk_prepare_enable(usb2->ref_clk); in bcm_ns_usb2_phy_init()
45 ref_clk_rate = clk_get_rate(usb2->ref_clk); in bcm_ns_usb2_phy_init()
48 err = -EINVAL; in bcm_ns_usb2_phy_init()
52 if (usb2->base) in bcm_ns_usb2_phy_init()
53 usb2ctl = readl(usb2->base); in bcm_ns_usb2_phy_init()
55 usb2ctl = readl(usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL); in bcm_ns_usb2_phy_init()
62 usb_pll_pdiv = 1 << 3; in bcm_ns_usb2_phy_init()
[all …]
/linux-6.12.1/drivers/usb/host/
Dfsl-mph-dr-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Setup platform devices needed by the Freescale multi-port host
4 * and/or dual-role USB controller modules based on the description
17 #include <linux/dma-mapping.h>
21 char *drivers[3]; /* drivers to instantiate for this mode */
28 .drivers = { "fsl-ehci", NULL, NULL, },
33 .drivers = { "fsl-usb2-otg", "fsl-ehci", "fsl-usb2-udc", },
38 .drivers = { "fsl-usb2-udc", NULL, NULL, },
84 const struct resource *res = ofdev->resource; in fsl_usb2_device_register()
85 unsigned int num = ofdev->num_resources; in fsl_usb2_device_register()
[all …]
/linux-6.12.1/drivers/usb/dwc3/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
64 AM437x use this IP for USB2/3 functionality.
78 tristate "PCIe-based Platforms"
86 tristate "Synopsys PCIe-based HAPS Platforms"
98 Support of USB2/3 functionality in TI Keystone2 and AM654 platforms.
109 Support USB2/3 functionality in Amlogic G12A platforms.
117 Support USB2/3 functionality in simple SoC integrations.
137 Some Qualcomm SoCs use DesignWare Core IP for USB2/3
149 NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
189 or dual-role mode.
/linux-6.12.1/Documentation/admin-guide/media/
Ddvb-usb-dw2102-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
3 dvb-usb-dw2102 cards list
8 .. flat-table::
9 :header-rows: 1
11 :stub-columns: 0
13 * - Card name
14 - USB IDs
15 * - DVBWorld DVB-C 3101 USB2.0
16 - 04b4:3101
17 * - DVBWorld DVB-S 2101 USB2.0
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8536si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
57 #size-cells = <2>;
[all …]
Dp1020si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
56 #size-cells = <2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
41 pll-supply = <&vdd_hdmi_pll>;
42 hdmi-supply = <&vdd_5v0_hdmi>;
[all …]
/linux-6.12.1/drivers/phy/amlogic/
Dphy-meson8b-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson8, Meson8b and GXBB USB2 PHY driver
22 #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
30 #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
50 /* bits [31:26], [24:21] and [15:3] seem to be read-only */
55 #define REG_ADP_BC_ID_PULLUP BIT(3)
84 #define REG_DBG_UART_BYPASS_DM_DATA BIT(3)
94 #define REG_TEST_DATA_IN_MASK GENMASK(3, 0)
105 #define REG_TUNE_TX_HSXV_TUNE_MASK GENMASK(3, 2)
146 if (!IS_ERR_OR_NULL(priv->reset)) { in phy_meson8b_usb2_power_on()
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm47094-dlink-dir-890l.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device tree for D-Link DIR-890L
4 * D-Link calls this board "WRGAC36"
5 * this router has the same looks and form factor as D-Link DIR-885L.
7 * Some differences from DIR-885L include a separate USB2 port, separate LEDs
8 * for USB2 and USB3, a separate VCC supply for the USB2 slot and no
13 * Based on the device tree for DIR-885L
18 /dts-v1/;
21 #include "bcm5301x-nand-cs0-bch1.dtsi"
24 compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708";
[all …]

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