Searched +full:usb +full:- +full:phy +full:- +full:controller (Results 1 – 25 of 1001) sorted by relevance
12345678910>>...41
/linux-6.12.1/Documentation/devicetree/bindings/phy/ |
D | realtek,usb2phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Realtek DHC SoCs USB 2.0 PHY 11 - Stanley Chang <stanley_chang@realtek.com> 14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs. 15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs 16 support multiple XHCI controllers. One PHY device node maps to one XHCI 17 controller. [all …]
|
D | realtek,usb3phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Realtek DHC SoCs USB 3.0 PHY 11 - Stanley Chang <stanley_chang@realtek.com> 14 Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs. 15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs 16 support multiple XHCI controllers. One PHY device node maps to one XHCI 17 controller. [all …]
|
D | marvell,armada-cp110-utmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Marvell Armada CP110/CP115 UTMI PHY 11 - Konstantin Porotchkin <kostap@marvell.com> 14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers. 15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device 16 controller. 17 The USB device controller can only be connected to a single UTMI PHY port [all …]
|
D | allwinner,sun8i-h3-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H3 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun8i-h3-usb-phy 20 - allwinner,sun50i-h616-usb-phy [all …]
|
D | allwinner,sun8i-r40-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner R40 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun8i-r40-usb-phy 22 - description: PHY Control registers [all …]
|
D | allwinner,sun6i-a31-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A31 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun6i-a31-usb-phy 22 - description: PHY Control registers [all …]
|
D | allwinner,sun8i-a83t-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A83t USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun8i-a83t-usb-phy 22 - description: PHY Control registers [all …]
|
D | allwinner,sun4i-a10-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A10 USB PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun4i-a10-usb-phy 20 - allwinner,sun7i-a20-usb-phy [all …]
|
D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra186 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
|
D | nvidia,tegra20-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra USB PHY 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 17 - items: 18 - enum: [all …]
|
D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra194 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
|
D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra210 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
|
D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra124 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
|
D | renesas,rcar-gen2-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car Gen2 USB PHY 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 15 - enum: 16 - renesas,usb-phy-r8a7742 # RZ/G1H 17 - renesas,usb-phy-r8a7743 # RZ/G1M 18 - renesas,usb-phy-r8a7744 # RZ/G1N [all …]
|
/linux-6.12.1/Documentation/devicetree/bindings/usb/ |
D | am33xx-usb.txt | 3 - compatible: ti,am33xx-usb 4 - reg: offset and length of the usbss register sets 5 - ti,hwmods : must be "usb_otg_hs" 8 at least a control module node, USB node and a PHY node. The second USB 9 node and its PHY node are optional. The DMA node is also optional. 13 - compatible: ti,am335x-usb-ctrl-module 14 - reg: offset and length of the "USB control registers" in the "Control 15 Module" block. A second offset and length for the USB wake up control 17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for 18 the USB wake up control register. [all …]
|
D | da8xx-usb.txt | 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms. 7 - compatible : Should be set to "ti,da830-musb". 9 - reg: Offset and length of the USB controller register set. 11 - interrupts: The USB interrupt number. 13 - interrupt-names: Should be set to "mc". 15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg". 17 - phys: Phandle for the PHY device 19 - phy-names: Should be "usb-phy" 21 - dmas: specifies the dma channels 23 - dma-names: specifies the names of the channels. Use "rxN" for receive [all …]
|
D | mediatek,mtu3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek USB3 DRD Controller 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 14 - $ref: usb-drd.yaml 17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is 23 - enum: 24 - mediatek,mt2712-mtu3 [all …]
|
D | nvidia,tegra-xudc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra XUSB device mode controller (XUDC) 10 The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and 11 USB 3.0 SuperSpeed protocols. 14 - Nagarjuna Kristam <nkristam@nvidia.com> 15 - JC Kuo <jckuo@nvidia.com> 16 - Thierry Reding <treding@nvidia.com> [all …]
|
/linux-6.12.1/drivers/phy/qualcomm/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Phy drivers for Qualcomm and Atheros platforms 6 tristate "Atheros AR71XX/9XXX USB PHY driver" 12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs. 15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver" 22 tristate "Qualcomm eDP PHY driver" 28 Enable this driver to support the Qualcomm eDP PHY found in various 32 tristate "Qualcomm IPQ4019 USB PHY driver" 36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. 39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver" [all …]
|
/linux-6.12.1/drivers/phy/st/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Phy drivers for STMicro platforms 6 tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407" 14 tristate "ST SPEAR1310-MIPHY driver" 21 tristate "ST SPEAR1340-MIPHY driver" 37 tristate "STMicroelectronics STM32 USB HS PHY Controller driver" 42 Enable this to support the High-Speed USB transceivers that are part 45 This driver controls the entire USB PHY block: the USB PHY controller 46 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is 47 used by an HS USB Host controller, and the second one is shared [all …]
|
/linux-6.12.1/drivers/phy/samsung/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Phy drivers for Samsung platforms 6 tristate "Exynos SoC series Display Port PHY driver" 12 Support for Display Port PHY found on Samsung Exynos SoCs. 15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver" 21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P 25 bool "Exynos PCIe PHY driver" 29 Enable PCIe PHY support for Exynos SoC series. 30 This driver provides PHY interface for Exynos PCIe controller. 33 tristate "Exynos SoC series UFS PHY driver" [all …]
|
/linux-6.12.1/drivers/phy/broadcom/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Phy drivers for Broadcom platforms 5 menu "PHY drivers for Broadcom platforms" 8 tristate "BCM63xx USBH PHY driver" 12 Enable this to support the BCM63xx USBH PHY driver. 16 tristate "Broadcom Cygnus PCIe PHY driver" 21 Enable this to support the Broadcom Cygnus PCIe PHY. 25 tristate "Broadcom Stingray USB PHY driver" 30 Enable this to support the Broadcom Stingray USB PHY 36 tristate "Broadcom Kona USB2 PHY Driver" [all …]
|
/linux-6.12.1/drivers/phy/socionext/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # PHY drivers for Socionext platforms. 7 tristate "UniPhier USB2 PHY driver" 13 Enable this to support USB PHY implemented on USB2 controller 15 with USB 2.0 PHY that is part of the UniPhier SoC. 16 In case of Pro4, it is necessary to specify this USB2 PHY instead 17 of USB3 HS-PHY. 20 tristate "UniPhier USB3 PHY driver" 25 Enable this to support USB PHY implemented in USB3 controller 26 on UniPhier SoCs. This controller supports USB3.0 and lower speed. [all …]
|
/linux-6.12.1/drivers/usb/host/ |
D | ehci-orion.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * drivers/usb/host/ehci-orion.c 13 #include <linux/platform_data/usb-ehci-orion.h> 15 #include <linux/phy/phy.h> 16 #include <linux/usb.h> 17 #include <linux/usb/hcd.h> 19 #include <linux/dma-mapping.h> 23 #define rdl(off) readl_relaxed(hcd->regs + (off)) 24 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off)) 59 #define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv) [all …]
|
/linux-6.12.1/drivers/usb/chipidea/ |
D | ci_hdrc_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <linux/usb.h> 15 #include <linux/usb/chipidea.h> 16 #include <linux/usb/hcd.h> 17 #include <linux/usb/of.h> 18 #include <linux/usb/phy.h> 31 struct usb_phy *phy; member 77 .compatible = "nvidia,tegra20-ehci", 80 .compatible = "nvidia,tegra30-ehci", 83 .compatible = "nvidia,tegra20-udc", [all …]
|
12345678910>>...41