Searched +full:uniphier +full:- +full:pro5 +full:- +full:pcie +full:- +full:ep (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Socionext UniPhier PCIe endpoint controller10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare11 PCI core. It shares common features with the PCIe DesignWare core and13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>21 - socionext,uniphier-pro5-pcie-ep[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier Pro5 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/interrupt-controller/arm-gic.h>11 compatible = "socionext,uniphier-pro5";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";[all …]
1 # SPDX-License-Identifier: GPL-2.03 menu "DesignWare-based PCIe controllers"18 bool "Amazon Annapurna Labs PCIe controller"24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare27 required only for DT-based platforms. ACPI platforms with the28 Annapurna Labs PCIe controller don't need to enable this.31 tristate "Amlogic Meson PCIe controller"38 and therefore the driver re-uses the DesignWare core functions to45 bool "Axis ARTPEC-6 PCIe controller (host mode)"[all …]
1 // SPDX-License-Identifier: GPL-2.03 * PCIe endpoint controller driver for UniPhier SoCs20 #include "pcie-designware.h"88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()113 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()120 /* set EP mode */ in uniphier_pcie_pro5_init_ep()121 val = readl(priv->base + PCL_MODE); in uniphier_pcie_pro5_init_ep()[all …]