bindings/pci/socionext%2Cuniphier-pcie-ep.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10   UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11   PCI core. It shares common features with the PCIe DesignWare core and
13   Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21       - socionext,uniphier-pro5-pcie-ep
22       - socionext,uniphier-nx1-pcie-ep
28   reg-names:
31       - const: dbi
32       - const: dbi2
33       - const: link
34       - const: addr_space
35       - const: atu
41   clock-names:
49   reset-names:
53   num-ib-windows:
56   num-ob-windows:
59   num-lanes: true
64   phy-names:
65     const: pcie-phy
68   - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
69   - if:
73             const: socionext,uniphier-pro5-pcie-ep
78         reg-names:
82         clock-names:
84             - const: gio
85             - const: link
88         reset-names:
90             - const: gio
91             - const: link
96         reg-names:
100         clock-names:
104         reset-names:
108   - compatible
109   - reg
110   - reg-names
111   - clocks
112   - clock-names
113   - resets
114   - reset-names
119   - |
120     pcie_ep: pcie-ep@66000000 {
121         compatible = "socionext,uniphier-pro5-pcie-ep";
122         reg-names = "dbi", "dbi2", "link", "addr_space";
125         clock-names = "gio", "link";
127         reset-names = "gio", "link";
129         num-ib-windows = <16>;
130         num-ob-windows = <16>;
131         num-lanes = <4>;
132         phy-names = "pcie-phy";