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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
[all …]
Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe host controller
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
[all …]
/linux-6.12.1/drivers/phy/socionext/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 tristate "UniPhier USB2 PHY driver"
14 on UniPhier SoCs. This driver provides interface to interact
15 with USB 2.0 PHY that is part of the UniPhier SoC.
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
29 tristate "Uniphier PHY driver for PCIe controller"
35 Enable this to support PHY implemented in PCIe controller
36 on UniPhier SoCs. This driver supports LD20 and PXs3 SoCs.
[all …]
Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
80 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
81 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
87 u32 val = readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_read()
126 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
129 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
136 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
138 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_PHY_UNIPHIER_USB2) += phy-uniphier-usb2.o
7 obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o
8 obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o
9 obj-$(CONFIG_PHY_UNIPHIER_AHCI) += phy-uniphier-ahci.o
/linux-6.12.1/drivers/reset/
Dreset-uniphier.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/reset-controller.h>
22 #define UNIPHIER_RESET_ID_END ((unsigned int)(-1))
58 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
66 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
69 UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */
80 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
81 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
82 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
83 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
[all …]
/linux-6.12.1/drivers/pci/controller/dwc/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
[all …]
Dpcie-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
23 #include "pcie-designware.h"
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
[all …]
Dpcie-uniphier-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint controller driver for UniPhier SoCs
20 #include "pcie-designware.h"
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
113 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
121 val = readl(priv->base + PCL_MODE); in uniphier_pcie_pro5_init_ep()
123 writel(val, priv->base + PCL_MODE); in uniphier_pcie_pro5_init_ep()
[all …]
/linux-6.12.1/arch/arm/boot/dts/socionext/
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
[all …]
Duniphier-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier SoCs default pinctrl settings
5 // Copyright (C) 2015-2017 Socionext Inc.
59 pinctrl_ether_mii: ether-mii {
64 pinctrl_ether_rgmii: ether-rgmii {
69 pinctrl_ether_rmii: ether-rmii {
74 pinctrl_ether1_rgmii: ether1-rgmii {
79 pinctrl_ether1_rmii: ether1-rmii {
129 pinctrl_pcie: pcie {
130 groups = "pcie";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
Duniphier-pxs3-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 Reference Board
8 /dts-v1/;
9 #include "uniphier-pxs3.dtsi"
10 #include "uniphier-support-card.dtsi"
13 model = "UniPhier PXs3 Reference Board";
14 compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
17 stdout-path = "serial0:115200n8";
71 xirq4-hog {
72 gpio-hog;
[all …]
Duniphier-ld20-akebi96.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Derived from uniphier-ld20-global.dts.
7 // Copyright (C) 2015-2017 Socionext Inc.
8 // Copyright (C) 2019-2020 Linaro Ltd.
10 /dts-v1/;
11 #include <dt-bindings/gpio/uniphier-gpio.h>
12 #include "uniphier-ld20.dtsi"
16 compatible = "socionext,uniphier-ld20-akebi96",
17 "socionext,uniphier-ld20";
20 stdout-path = "serial0:115200n8";
[all …]
/linux-6.12.1/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
19 bool "Allwinner sunxi 64-bit SoC Family"
40 This enables support for Apple's in-house ARM SoC family, starting
74 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
77 This enables support for Broadcom BCA ARM-based broadband chipsets,
81 bool "Broadcom Set-Top-Box SoCs"
122 This enables support for the Microchip Sparx5 ARMv8-based
123 SoC family of TSN-capable gigabit switches.
125 The SparX-5 Ethernet switch family provides a rich set of
126 switching features such as advanced TCAM-based VLAN and QoS
[all …]
/linux-6.12.1/drivers/nvmem/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 calibration data required for the PCIe or the USB-C PHY.
41 be called nvmem-apple-efuses.
44 tristate "Broadcom On-Chip OTP Controller support"
53 will be called nvmem-bcm-ocotp.
73 will be called nvmem-imx-iim.
76 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
80 This is a driver for the On-Chip OTP Controller (OCOTP) available on
81 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
85 will be called nvmem-imx-ocotp.
[all …]
/linux-6.12.1/drivers/tty/serial/8250/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
23 non-standard serial ports, since the configuration information will
51 If you did not notice yet and/or you have userspace from pre-3.7, it
146 Note that serial ports on NetMos 9835 Multi-I/O cards are handled
150 tristate "8250/16550 Exar/Commtech PCI/PCIe device support"
156 422x PCIe serial cards that are not covered by the more generic
168 Say Y here to enable support for 16-bit PCMCIA serial devices,
170 multi-function Ethernet/modem cards. (PCMCIA- or PC-cards are
171 credit-card size devices often used with laptops.)
197 PCI enumeration and any ports that may be added at run-time
[all …]
/linux-6.12.1/drivers/i2c/busses/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
[all …]
/linux-6.12.1/drivers/irqchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
177 maps the internal interrupts sources to PCIe interrupt.
180 will be called irq-lan966x-oic.
221 bool "J-Core integrated AIC" if COMPILE_TEST
225 Support for the J-Core integrated AIC.
236 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
239 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
244 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
[all …]
/linux-6.12.1/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
285 clock. These multi-function devices have two (S2MPS14) or three
286 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_CLK_KUNIT_TEST) += clk-test.o
6 clk-test-y := clk_test.o \
8 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
9 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
10 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
11 obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) += clk-fixed-rate-test.o
12 clk-fixed-rate-test-y := clk-fixed-rate_test.o kunit_clk_fixed_rate_test.dtbo.o
[all …]
/linux-6.12.1/drivers/clk/uniphier/
Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
[all …]

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