Lines Matching +full:uniphier +full:- +full:pcie
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe endpoint controller driver for UniPhier SoCs
20 #include "pcie-designware.h"
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
113 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
121 val = readl(priv->base + PCL_MODE); in uniphier_pcie_pro5_init_ep()
123 writel(val, priv->base + PCL_MODE); in uniphier_pcie_pro5_init_ep()
126 val = readl(priv->base + PCL_APP_CLK_CTRL); in uniphier_pcie_pro5_init_ep()
128 writel(val, priv->base + PCL_APP_CLK_CTRL); in uniphier_pcie_pro5_init_ep()
131 val = readl(priv->base + PCL_RSTCTRL0); in uniphier_pcie_pro5_init_ep()
134 writel(val, priv->base + PCL_RSTCTRL0); in uniphier_pcie_pro5_init_ep()
146 val = readl(priv->base + PCL_MODE); in uniphier_pcie_nx1_init_ep()
148 writel(val, priv->base + PCL_MODE); in uniphier_pcie_nx1_init_ep()
151 val = readl(priv->base + PCL_APP_PM0); in uniphier_pcie_nx1_init_ep()
153 writel(val, priv->base + PCL_APP_PM0); in uniphier_pcie_nx1_init_ep()
156 val = readl(priv->base + PCL_PINCTRL0); in uniphier_pcie_nx1_init_ep()
161 writel(val, priv->base + PCL_PINCTRL0); in uniphier_pcie_nx1_init_ep()
168 val = readl(priv->base + PCL_PINCTRL0); in uniphier_pcie_nx1_init_ep()
170 writel(val, priv->base + PCL_PINCTRL0); in uniphier_pcie_nx1_init_ep()
179 ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status, in uniphier_pcie_nx1_wait_ep()
182 dev_err(priv->pci.dev, in uniphier_pcie_nx1_wait_ep()
227 val = readl(priv->base + PCL_APP_INTX); in uniphier_pcie_ep_raise_intx_irq()
229 writel(val, priv->base + PCL_APP_INTX); in uniphier_pcie_ep_raise_intx_irq()
235 writel(val, priv->base + PCL_APP_INTX); in uniphier_pcie_ep_raise_intx_irq()
248 | FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1); in uniphier_pcie_ep_raise_msi_irq()
249 writel(val, priv->base + PCL_APP_MSI0); in uniphier_pcie_ep_raise_msi_irq()
251 val = readl(priv->base + PCL_APP_MSI1); in uniphier_pcie_ep_raise_msi_irq()
253 writel(val, priv->base + PCL_APP_MSI1); in uniphier_pcie_ep_raise_msi_irq()
270 dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type); in uniphier_pcie_ep_raise_irq()
282 return &priv->data->features; in uniphier_pcie_get_features()
295 ret = clk_prepare_enable(priv->clk); in uniphier_pcie_ep_enable()
299 ret = clk_prepare_enable(priv->clk_gio); in uniphier_pcie_ep_enable()
303 ret = reset_control_deassert(priv->rst); in uniphier_pcie_ep_enable()
307 ret = reset_control_deassert(priv->rst_gio); in uniphier_pcie_ep_enable()
311 if (priv->data->init) in uniphier_pcie_ep_enable()
312 priv->data->init(priv); in uniphier_pcie_ep_enable()
316 ret = phy_init(priv->phy); in uniphier_pcie_ep_enable()
322 if (priv->data->wait) { in uniphier_pcie_ep_enable()
323 ret = priv->data->wait(priv); in uniphier_pcie_ep_enable()
331 phy_exit(priv->phy); in uniphier_pcie_ep_enable()
333 reset_control_assert(priv->rst_gio); in uniphier_pcie_ep_enable()
335 reset_control_assert(priv->rst); in uniphier_pcie_ep_enable()
337 clk_disable_unprepare(priv->clk_gio); in uniphier_pcie_ep_enable()
339 clk_disable_unprepare(priv->clk); in uniphier_pcie_ep_enable()
351 struct device *dev = &pdev->dev; in uniphier_pcie_ep_probe()
357 return -ENOMEM; in uniphier_pcie_ep_probe()
359 priv->data = of_device_get_match_data(dev); in uniphier_pcie_ep_probe()
360 if (WARN_ON(!priv->data)) in uniphier_pcie_ep_probe()
361 return -EINVAL; in uniphier_pcie_ep_probe()
363 priv->pci.dev = dev; in uniphier_pcie_ep_probe()
364 priv->pci.ops = &dw_pcie_ops; in uniphier_pcie_ep_probe()
366 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); in uniphier_pcie_ep_probe()
367 if (IS_ERR(priv->base)) in uniphier_pcie_ep_probe()
368 return PTR_ERR(priv->base); in uniphier_pcie_ep_probe()
370 if (priv->data->has_gio) { in uniphier_pcie_ep_probe()
371 priv->clk_gio = devm_clk_get(dev, "gio"); in uniphier_pcie_ep_probe()
372 if (IS_ERR(priv->clk_gio)) in uniphier_pcie_ep_probe()
373 return PTR_ERR(priv->clk_gio); in uniphier_pcie_ep_probe()
375 priv->rst_gio = devm_reset_control_get_shared(dev, "gio"); in uniphier_pcie_ep_probe()
376 if (IS_ERR(priv->rst_gio)) in uniphier_pcie_ep_probe()
377 return PTR_ERR(priv->rst_gio); in uniphier_pcie_ep_probe()
380 priv->clk = devm_clk_get(dev, "link"); in uniphier_pcie_ep_probe()
381 if (IS_ERR(priv->clk)) in uniphier_pcie_ep_probe()
382 return PTR_ERR(priv->clk); in uniphier_pcie_ep_probe()
384 priv->rst = devm_reset_control_get_shared(dev, "link"); in uniphier_pcie_ep_probe()
385 if (IS_ERR(priv->rst)) in uniphier_pcie_ep_probe()
386 return PTR_ERR(priv->rst); in uniphier_pcie_ep_probe()
388 priv->phy = devm_phy_optional_get(dev, "pcie-phy"); in uniphier_pcie_ep_probe()
389 if (IS_ERR(priv->phy)) { in uniphier_pcie_ep_probe()
390 ret = PTR_ERR(priv->phy); in uniphier_pcie_ep_probe()
401 priv->pci.ep.ops = &uniphier_pcie_ep_ops; in uniphier_pcie_ep_probe()
402 ret = dw_pcie_ep_init(&priv->pci.ep); in uniphier_pcie_ep_probe()
406 ret = dw_pcie_ep_init_registers(&priv->pci.ep); in uniphier_pcie_ep_probe()
409 dw_pcie_ep_deinit(&priv->pci.ep); in uniphier_pcie_ep_probe()
413 pci_epc_init_notify(priv->pci.ep.epc); in uniphier_pcie_ep_probe()
456 .compatible = "socionext,uniphier-pro5-pcie-ep",
460 .compatible = "socionext,uniphier-nx1-pcie-ep",
469 .name = "uniphier-pcie-ep",