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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
19 - ti,am642-icssg-prueth # for AM64x SoC family
20 - ti,am654-icssg-prueth # for AM65x SoC family
21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
32 dma-names:
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Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
22 Complex (UDMA-P) controller.
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
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/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/linux-6.12.1/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
17 #include <linux/phy/phy-dp.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp-dp-phy.h"
26 #include "phy-qcom-qmp-qserdes-com-v4.h"
27 #include "phy-qcom-qmp-qserdes-com-v6.h"
30 #define DP_PHY_CFG 0x0010
31 #define DP_PHY_CFG_1 0x0014
32 #define DP_PHY_PD_CTL 0x001c
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/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-iot2050-common-pg1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2021-2023
11 #include "k3-am65-iot2050-dp.dtsi"
18 no-1-8-v;
46 compatible = "ti,am654-sr1-icssg-prueth";
49 firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
50 "ti-pruss/am65x-rtu0-prueth-fw.elf",
51 "ti-pruss/am65x-pru1-prueth-fw.elf",
52 "ti-pruss/am65x-rtu1-prueth-fw.elf";
54 ti,pruss-gp-mux-sel = <2>, /* MII mode */
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Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
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Dk3-am654-icssg2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
17 ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
20 /* Ethernet node on PRU-ICSSG2 */
21 icssg2_eth: icssg2-eth {
22 compatible = "ti,am654-icssg-prueth";
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Dk3-am642-phyboard-electra-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phyboard-am64x
13 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
[all …]
Dk3-am65-iot2050-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2024
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/net/ti-dp83867.h>
36 stdout-path = "serial3:115200n8";
39 reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
44 secure_ddr: secure-ddr@9e800000 {
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Dk3-am642-sr-som.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
7 #include <dt-bindings/net/ti-dp83869.h>
11 compatible = "solidrun,am642-sr-som", "ti,am642";
24 stdout-path = "serial2:115200n8";
29 compatible = "ti,am642-icssg-prueth";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>;
35 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
36 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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Dk3-am642-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
14 #include "k3-serdes.h"
17 compatible = "ti,am642-evm", "ti,am642";
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
11 reg = <0 0x2c000000 0 0x1000000>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
17 reg = <0x2d000000 0x20000>;
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
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/linux-6.12.1/sound/firewire/dice/
Ddice-alesis.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-alesis.c - a part of driver for DICE based devices
12 {6, 6, 4}, /* Tx0 = Analog + S/PDIF. */
13 {8, 4, 0}, /* Tx1 = ADAT1. */
18 {10, 10, 4}, /* Tx0 = Analog + S/PDIF. */
19 {16, 4, 0}, /* Tx1 = ADAT1 + ADAT2 (available at low rate). */
31 if (err < 0) in snd_dice_detect_alesis_formats()
36 memcpy(dice->tx_pcm_chs, alesis_io14_tx_pcm_chs, in snd_dice_detect_alesis_formats()
40 memcpy(dice->tx_pcm_chs, alesis_io26_tx_pcm_chs, in snd_dice_detect_alesis_formats()
45 for (i = 0; i < SND_DICE_RATE_MODE_COUNT; ++i) in snd_dice_detect_alesis_formats()
[all …]
/linux-6.12.1/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4114_REG_PWRDN 0x00 /* power down */
12 #define AK4114_REG_FORMAT 0x01 /* format control */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
17 #define AK4114_REG_RCS0 0x06 /* receiver status 0 */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
[all …]
/linux-6.12.1/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
14 #define s0 0
22 3-way twofish
43 #define CD0 0x0(%rsp)
44 #define CD1 0x8(%rsp)
45 #define CD2 0x10(%rsp)
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
23 - qcom,sc8280xp-edp-phy
24 - qcom,x1e80100-dp-phy
[all …]
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
14 const: 0
18 - google,gs101-ufs-phy
19 - samsung,exynos7-ufs-phy
20 - samsung,exynosautov9-ufs-phy
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/linux-6.12.1/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
57 - desc-sg[i]: i-th descriptor, transferring the i-th sg
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Domap-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Aswath Govindraju <a-govindraju@ti.com>
13 - $ref: spi-controller.yaml#
18 - items:
19 - enum:
20 - ti,am654-mcspi
21 - ti,am4372-mcspi
[all …]
/linux-6.12.1/drivers/media/platform/amphion/
Dvpu_mbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
31 return -EINVAL; in vpu_mbox_request_channel()
32 if (mbox->ch) in vpu_mbox_request_channel()
33 return 0; in vpu_mbox_request_channel()
35 cl = &mbox->cl; in vpu_mbox_request_channel()
36 cl->dev = dev; in vpu_mbox_request_channel()
37 if (mbox->block) { in vpu_mbox_request_channel()
38 cl->tx_block = true; in vpu_mbox_request_channel()
39 cl->tx_tout = 1000; in vpu_mbox_request_channel()
[all …]

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