Searched +full:tx +full:- +full:fifo +full:- +full:max +full:- +full:num (Results 1 – 25 of 195) sorted by relevance
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| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| /linux-6.12.1/Documentation/devicetree/bindings/spi/ |
| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
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| /linux-6.12.1/drivers/net/ethernet/sun/ |
| D | sunbmac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
43 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
50 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
51 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
76 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
77 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
78 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
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| D | sunhme.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
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| /linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | ampdu.c | 27 /* max number of mpdus in an ampdu */
29 /* max number of mpdus in an ampdu to a legacy */
31 /* max Tx ba window size (in pdu) */
33 /* default Tx ba window size (in pdu) */
37 /* max Rx ba window size (in pdu) */
39 /* max dur of tx ampdu (in msec) */
41 /* default tx retry limit */
43 /* default tx retry limit at reg rate */
49 /* max # of mpdus released at a time */
52 #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | eiger.dts | 11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
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| D | arches.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
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| D | taishan.dts | 13 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <1>;
20 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <800000000>; // 800MHz
38 timebase-frequency = <0>; // Filled in by zImage
39 i-cache-line-size = <50>;
40 d-cache-line-size = <50>;
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| D | fsp2.dts | 12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
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| D | bamboo.dts | 14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
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| D | sam440ep.dts | 16 /dts-v1/;
19 #address-cells = <2>;
20 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
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| D | glacier.dts | 4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
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| D | rainier.dts | 15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
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| D | yosemite.dts | 12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
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| D | ebony.dts | 14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; // Filled in by zImage
39 timebase-frequency = <0>; // Filled in by zImage
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
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| /linux-6.12.1/Documentation/netlink/specs/ |
| D | rt_link.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 name: rt-link
4 protocol: netlink-raw
11 -
12 name: ifinfo-flags
15 -
17 -
19 -
21 -
23 -
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| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
130 * struct st_i2c_timings - per-Mode tuning parameters
152 * struct st_i2c_client - client specific data
153 * @addr: 8-bit target addr, including r/w bit
170 * struct st_i2c_dev - private data of the controller
181 * @busy: I2C transfer on-going
211 * compatible with some out-of-spec devices,
240 * Counter only counts up to 7 but fifo size is 8... in st_i2c_flush_rx_fifo()
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| D | i2c-qup.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
77 /* Most significant word offset in FIFO port */
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
148 /* Max data length for each DATARD tags */
150 /* TAG length for DATA READ in RX FIFO */
160 * tx_tag_len: tx tag length for current block
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
166 * tx_fifo_data_pos: current byte number in TX FIFO word
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| D | i2c-pnx.c | 7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
36 int order; /* RX Bytes to order via TX */
82 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
83 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
84 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
85 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
86 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
87 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
88 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
89 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
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| D | i2c-xiic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
63 * @tx_pos: Current pos in TX message
67 * @endianness: big/little-endian byte order
68 * @clk: Pointer to AXI4-lite input clock
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| /linux-6.12.1/drivers/net/can/m_can/ |
| D | m_can.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
8 * https://github.com/linux-can/can-doc/tree/master/m_can
226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
243 /* Tx Buffer Configuration (TXBC) */
247 /* Tx FIFO/Queue Status (TXFQS) */
253 /* Tx Buffer Element Size Configuration (TXESC) */
257 /* Tx Event FIFO Configuration (TXEFC) */
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| /linux-6.12.1/drivers/usb/gadget/udc/ |
| D | snps_udc_core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
63 * slave mode: pending bytes in rx fifo after nyet,
76 /* set_rde -- Is used to control enabling of RX DMA. Problem is
79 * when OUT data reaches the fifo but no request was queued yet.
82 * in the FIFO (important for not blocking control traffic).
85 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 1 == timer function will look whether FIFO has data
90 static int set_rde = -1;
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| /linux-6.12.1/drivers/spi/ |
| D | spi-hisi-kunpeng.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 // This code is based on spi-dw-core.c.
26 #define HISI_SPI_FIFOC 0x0c /* fifo level control register */
57 #define SR_TXE BIT(0) /* Transmit FIFO empty */
58 #define SR_TXNF BIT(1) /* Transmit FIFO not full */
59 #define SR_RXNE BIT(2) /* Receive FIFO not empty */
60 #define SR_RXF BIT(3) /* Receive FIFO full */
129 u32 fifo_len; /* depth of the FIFO buffer */
132 const void *tx; member
167 host = container_of(hs->dev, struct spi_controller, dev); in hisi_spi_debugfs_init()
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| /linux-6.12.1/arch/nios2/boot/dts/ |
| D | 10m50_devboard.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
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